Генератор Verilog для прямого преобразователя в базис вида (2ⁿ-1, 2ⁿ, 2ⁿ+1)

Прямой преобразователь для базиса: (7, 8, 9). Значение на входе [0;504)

module forward_converter (x, x_mod9, x_mod8, x_mod7);
	input  [8:0] x;
	output [3:0] x_mod9;
	output [2:0] x_mod8;
	output [2:0] x_mod7;

	wire [2:0] x0;
	wire [2:0] x1;
	wire [2:0] x2;
	assign x0 = x[2:0];
	assign x1 = x[5:3];
	assign x2 = x[8:6];
	wire [4:0] x_prom_7;
	assign x_prom_7 = x0 + x1 + x2 ;
	mod_7_21 mod1(x_prom_7, x_mod7);
	wire [4:0] x_prom_9;
	assign x_prom_9 = x0 + 4'd9 - x1 + x2 + 0;
	mod_9_25 mod2(x_prom_9, x_mod9);
	assign x_mod8 = x[2:0];
endmodule

module mod_7_21 (in, out);
	input [4:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 0;
		8: out = 1;
		9: out = 2;
		10: out = 3;
		11: out = 4;
		12: out = 5;
		13: out = 6;
		14: out = 0;
		15: out = 1;
		16: out = 2;
		17: out = 3;
		18: out = 4;
		19: out = 5;
		20: out = 6;
		21: out = 0;
		default: out = 0;
	endcase
	end
endmodule

module mod_9_25 (in, out);
	input [4:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 7;
		8: out = 8;
		9: out = 0;
		10: out = 1;
		11: out = 2;
		12: out = 3;
		13: out = 4;
		14: out = 5;
		15: out = 6;
		16: out = 7;
		17: out = 8;
		18: out = 0;
		19: out = 1;
		20: out = 2;
		21: out = 3;
		22: out = 4;
		23: out = 5;
		24: out = 6;
		25: out = 7;
		default: out = 0;
	endcase
	end
endmodule

module atest_bench();
	reg [8:0] x;
	wire [3:0] x1;
	wire [2:0] x2;
	wire [2:0] x3;
			
	integer i, j, k, l, m, n;
	reg dummy;
	integer fori;
	
	forward_converter r1(x, x1, x2, x3);
	
	initial
	begin
	for (fori = 0; fori <= 9'd504; fori = fori + 1)
	begin
		x = fori;
		#1 dummy = 1;
		l = fori%4'd9;
		m = fori%4'd8;
		n = fori%3'd7;
		$display ("!!! Input = (%d) Res = (%d, %d, %d) Expect = (%d, %d, %d)", fori, x1, x2, x3, l, m, n);
		i = x1;
		j = x2;
		k = x3;
		if (i != l || j != m || k != n)
		begin
			$display ("!!! Error (%d, %d, %d, %d)!!!", fori, i, j, k);
		end
		#1 dummy = 1;
	end
	end
endmodule

Генератор Verilog для прямого преобразователя в базис вида (2n-1, 2n, 2n+1)

Генератор Verilog для прямого преобразователя в базис вида (2ⁿ-1, 2ⁿ, 2ⁿ+1)