Verilog generator for RNS mod 2^n-1 adder
Choose n for module 2
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-1 (from 3 to 128):
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Simple implementation with double addition and comparison:
// Sum modulo (2^3 - 1) = 7 module sum_modulo_7 (in1, in2, out); input [2:0] in1; input [2:0] in2; output reg [2:0] out; wire [3:0] data; wire [3:0] data2; assign data = in1 + in2; assign data2 = in1 + in2 + 1; always @(*) begin if (data2[3] == 1) out <= data2[2:0]; else out <= data[2:0]; end endmodule
Test Bench:
module atest_bench(); reg [2:0] in1; reg [2:0] in2; wire [2:0] out; integer i, j, l, m, t; reg dummy; wire complete; integer fori, forj; sum_modulo_7 sm1(in1, in2, out); initial begin for (fori = 0; fori < 7; fori = fori + 1) begin for (forj = 0; forj < 7; forj = forj + 1) begin in1 = fori; in2 = forj; m = (fori + forj) % 7; #1 dummy = 1; $display ("!!! IN1=(%d) IN2=(%d) Res=(%d) Expect=(%d)", fori, forj, out, m); l = out; if (l != m) begin $display ("!!! Error (%d, %d)!!!", l, m); end #1 dummy = 1; end end end endmodule
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