Генератор Verilog описания для SAD-процессора

Размеры SAD: 4х4
Бит на пиксель: 8
Максимальное значение суммы: 4080

module sad_processor (pixel_a_0_0, pixel_b_0_0, pixel_a_0_1, pixel_b_0_1, pixel_a_0_2, pixel_b_0_2, pixel_a_0_3, pixel_b_0_3, pixel_a_1_0, pixel_b_1_0, pixel_a_1_1, pixel_b_1_1, pixel_a_1_2, pixel_b_1_2, pixel_a_1_3, pixel_b_1_3, pixel_a_2_0, pixel_b_2_0, pixel_a_2_1, pixel_b_2_1, pixel_a_2_2, pixel_b_2_2, pixel_a_2_3, pixel_b_2_3, pixel_a_3_0, pixel_b_3_0, pixel_a_3_1, pixel_b_3_1, pixel_a_3_2, pixel_b_3_2, pixel_a_3_3, pixel_b_3_3, out);
	input [7:0] pixel_a_0_0;
	input [7:0] pixel_b_0_0;
	wire [7:0] sub_res_0_0;
	input [7:0] pixel_a_0_1;
	input [7:0] pixel_b_0_1;
	wire [7:0] sub_res_0_1;
	input [7:0] pixel_a_0_2;
	input [7:0] pixel_b_0_2;
	wire [7:0] sub_res_0_2;
	input [7:0] pixel_a_0_3;
	input [7:0] pixel_b_0_3;
	wire [7:0] sub_res_0_3;
	input [7:0] pixel_a_1_0;
	input [7:0] pixel_b_1_0;
	wire [7:0] sub_res_1_0;
	input [7:0] pixel_a_1_1;
	input [7:0] pixel_b_1_1;
	wire [7:0] sub_res_1_1;
	input [7:0] pixel_a_1_2;
	input [7:0] pixel_b_1_2;
	wire [7:0] sub_res_1_2;
	input [7:0] pixel_a_1_3;
	input [7:0] pixel_b_1_3;
	wire [7:0] sub_res_1_3;
	input [7:0] pixel_a_2_0;
	input [7:0] pixel_b_2_0;
	wire [7:0] sub_res_2_0;
	input [7:0] pixel_a_2_1;
	input [7:0] pixel_b_2_1;
	wire [7:0] sub_res_2_1;
	input [7:0] pixel_a_2_2;
	input [7:0] pixel_b_2_2;
	wire [7:0] sub_res_2_2;
	input [7:0] pixel_a_2_3;
	input [7:0] pixel_b_2_3;
	wire [7:0] sub_res_2_3;
	input [7:0] pixel_a_3_0;
	input [7:0] pixel_b_3_0;
	wire [7:0] sub_res_3_0;
	input [7:0] pixel_a_3_1;
	input [7:0] pixel_b_3_1;
	wire [7:0] sub_res_3_1;
	input [7:0] pixel_a_3_2;
	input [7:0] pixel_b_3_2;
	wire [7:0] sub_res_3_2;
	input [7:0] pixel_a_3_3;
	input [7:0] pixel_b_3_3;
	wire [7:0] sub_res_3_3;
	output [11:0] out;

	substruct sub0_0(pixel_a_0_0, pixel_b_0_0, sub_res_0_0);
	substruct sub0_1(pixel_a_0_1, pixel_b_0_1, sub_res_0_1);
	substruct sub0_2(pixel_a_0_2, pixel_b_0_2, sub_res_0_2);
	substruct sub0_3(pixel_a_0_3, pixel_b_0_3, sub_res_0_3);
	substruct sub1_0(pixel_a_1_0, pixel_b_1_0, sub_res_1_0);
	substruct sub1_1(pixel_a_1_1, pixel_b_1_1, sub_res_1_1);
	substruct sub1_2(pixel_a_1_2, pixel_b_1_2, sub_res_1_2);
	substruct sub1_3(pixel_a_1_3, pixel_b_1_3, sub_res_1_3);
	substruct sub2_0(pixel_a_2_0, pixel_b_2_0, sub_res_2_0);
	substruct sub2_1(pixel_a_2_1, pixel_b_2_1, sub_res_2_1);
	substruct sub2_2(pixel_a_2_2, pixel_b_2_2, sub_res_2_2);
	substruct sub2_3(pixel_a_2_3, pixel_b_2_3, sub_res_2_3);
	substruct sub3_0(pixel_a_3_0, pixel_b_3_0, sub_res_3_0);
	substruct sub3_1(pixel_a_3_1, pixel_b_3_1, sub_res_3_1);
	substruct sub3_2(pixel_a_3_2, pixel_b_3_2, sub_res_3_2);
	substruct sub3_3(pixel_a_3_3, pixel_b_3_3, sub_res_3_3);
	wire [8:0] sum_int_8_0;
	sum_8bit sm_8_0(sub_res_0_0 , sub_res_0_1, sum_int_8_0);
	wire [8:0] sum_int_8_1;
	sum_8bit sm_8_2(sub_res_0_2 , sub_res_0_3, sum_int_8_1);
	wire [8:0] sum_int_8_2;
	sum_8bit sm_8_4(sub_res_1_0 , sub_res_1_1, sum_int_8_2);
	wire [8:0] sum_int_8_3;
	sum_8bit sm_8_6(sub_res_1_2 , sub_res_1_3, sum_int_8_3);
	wire [8:0] sum_int_8_4;
	sum_8bit sm_8_8(sub_res_2_0 , sub_res_2_1, sum_int_8_4);
	wire [8:0] sum_int_8_5;
	sum_8bit sm_8_10(sub_res_2_2 , sub_res_2_3, sum_int_8_5);
	wire [8:0] sum_int_8_6;
	sum_8bit sm_8_12(sub_res_3_0 , sub_res_3_1, sum_int_8_6);
	wire [8:0] sum_int_8_7;
	sum_8bit sm_8_14(sub_res_3_2 , sub_res_3_3, sum_int_8_7);
	wire [9:0] sum_int_9_0;
	sum_9bit sm_9_0(sum_int_8_0 , sum_int_8_1, sum_int_9_0);
	wire [9:0] sum_int_9_1;
	sum_9bit sm_9_2(sum_int_8_2 , sum_int_8_3, sum_int_9_1);
	wire [9:0] sum_int_9_2;
	sum_9bit sm_9_4(sum_int_8_4 , sum_int_8_5, sum_int_9_2);
	wire [9:0] sum_int_9_3;
	sum_9bit sm_9_6(sum_int_8_6 , sum_int_8_7, sum_int_9_3);
	wire [10:0] sum_int_10_0;
	sum_10bit sm_10_0(sum_int_9_0 , sum_int_9_1, sum_int_10_0);
	wire [10:0] sum_int_10_1;
	sum_10bit sm_10_2(sum_int_9_2 , sum_int_9_3, sum_int_10_1);
	sum_11bit sm_11_0(sum_int_10_0 , sum_int_10_1, out);
endmodule
	
module substruct(in1, in2, out);
	input [7:0] in1;
	input [7:0] in2;
	output reg [7:0] out;
	
	always @(*)
	begin
		if (in1 < in2)
			out <= in2 - in1;
		else
			out <= in1 - in2;
	end
	
endmodule

			
module sum_8bit(in1, in2, out);
	input [7:0] in1;
	input [7:0] in2;
	output [8:0] out;
	
	assign out = in1 + in2;
	
endmodule

		
module sum_9bit(in1, in2, out);
	input [8:0] in1;
	input [8:0] in2;
	output [9:0] out;
	
	assign out = in1 + in2;
	
endmodule

		
module sum_10bit(in1, in2, out);
	input [9:0] in1;
	input [9:0] in2;
	output [10:0] out;
	
	assign out = in1 + in2;
	
endmodule

		
module sum_11bit(in1, in2, out);
	input [10:0] in1;
	input [10:0] in2;
	output [11:0] out;
	
	assign out = in1 + in2;
	
endmodule

module atest_bench();
	reg [7:0] pixel_a_0_0;
	reg [7:0] pixel_b_0_0;
	reg [7:0] pixel_a_0_1;
	reg [7:0] pixel_b_0_1;
	reg [7:0] pixel_a_0_2;
	reg [7:0] pixel_b_0_2;
	reg [7:0] pixel_a_0_3;
	reg [7:0] pixel_b_0_3;
	reg [7:0] pixel_a_1_0;
	reg [7:0] pixel_b_1_0;
	reg [7:0] pixel_a_1_1;
	reg [7:0] pixel_b_1_1;
	reg [7:0] pixel_a_1_2;
	reg [7:0] pixel_b_1_2;
	reg [7:0] pixel_a_1_3;
	reg [7:0] pixel_b_1_3;
	reg [7:0] pixel_a_2_0;
	reg [7:0] pixel_b_2_0;
	reg [7:0] pixel_a_2_1;
	reg [7:0] pixel_b_2_1;
	reg [7:0] pixel_a_2_2;
	reg [7:0] pixel_b_2_2;
	reg [7:0] pixel_a_2_3;
	reg [7:0] pixel_b_2_3;
	reg [7:0] pixel_a_3_0;
	reg [7:0] pixel_b_3_0;
	reg [7:0] pixel_a_3_1;
	reg [7:0] pixel_b_3_1;
	reg [7:0] pixel_a_3_2;
	reg [7:0] pixel_b_3_2;
	reg [7:0] pixel_a_3_3;
	reg [7:0] pixel_b_3_3;
	wire [11:0] out;

	
	integer i, j, l, m, t;
	reg dummy;
	wire complete;
	integer fori;
	
	sad_processor r1 (pixel_a_0_0, pixel_b_0_0, pixel_a_0_1, pixel_b_0_1, pixel_a_0_2, pixel_b_0_2, pixel_a_0_3, pixel_b_0_3, pixel_a_1_0, pixel_b_1_0, pixel_a_1_1, pixel_b_1_1, pixel_a_1_2, pixel_b_1_2, pixel_a_1_3, pixel_b_1_3, pixel_a_2_0, pixel_b_2_0, pixel_a_2_1, pixel_b_2_1, pixel_a_2_2, pixel_b_2_2, pixel_a_2_3, pixel_b_2_3, pixel_a_3_0, pixel_b_3_0, pixel_a_3_1, pixel_b_3_1, pixel_a_3_2, pixel_b_3_2, pixel_a_3_3, pixel_b_3_3, out);
		
	initial
	begin
	pixel_a_0_0 = 91;
	pixel_b_0_0 = 69;
	pixel_a_0_1 = 126;
	pixel_b_0_1 = 136;
	pixel_a_0_2 = 235;
	pixel_b_0_2 = 94;
	pixel_a_0_3 = 212;
	pixel_b_0_3 = 62;
	pixel_a_1_0 = 188;
	pixel_b_1_0 = 31;
	pixel_a_1_1 = 235;
	pixel_b_1_1 = 17;
	pixel_a_1_2 = 66;
	pixel_b_1_2 = 166;
	pixel_a_1_3 = 149;
	pixel_b_1_3 = 174;
	pixel_a_2_0 = 73;
	pixel_b_2_0 = 69;
	pixel_a_2_1 = 242;
	pixel_b_2_1 = 123;
	pixel_a_2_2 = 4;
	pixel_b_2_2 = 166;
	pixel_a_2_3 = 4;
	pixel_b_2_3 = 48;
	pixel_a_3_0 = 17;
	pixel_b_3_0 = 226;
	pixel_a_3_1 = 125;
	pixel_b_3_1 = 60;
	pixel_a_3_2 = 130;
	pixel_b_3_2 = 211;
	pixel_a_3_3 = 243;
	pixel_b_3_3 = 221;
	#1 dummy = 1;
	fori = 1529;
	$display ("!!! Res=(%d) Expect=(%d)", out, fori);
	l = out;
	if (l != fori)
	begin
		$display ("!!! Error (%d, %d)!!!", fori, l);
	end
	#1 dummy = 1;
		pixel_a_0_0 = 24;
	pixel_b_0_0 = 113;
	pixel_a_0_1 = 101;
	pixel_b_0_1 = 3;
	pixel_a_0_2 = 207;
	pixel_b_0_2 = 57;
	pixel_a_0_3 = 65;
	pixel_b_0_3 = 139;
	pixel_a_1_0 = 88;
	pixel_b_1_0 = 44;
	pixel_a_1_1 = 157;
	pixel_b_1_1 = 155;
	pixel_a_1_2 = 210;
	pixel_b_1_2 = 50;
	pixel_a_1_3 = 73;
	pixel_b_1_3 = 27;
	pixel_a_2_0 = 119;
	pixel_b_2_0 = 59;
	pixel_a_2_1 = 150;
	pixel_b_2_1 = 124;
	pixel_a_2_2 = 225;
	pixel_b_2_2 = 154;
	pixel_a_2_3 = 172;
	pixel_b_2_3 = 242;
	pixel_a_3_0 = 125;
	pixel_b_3_0 = 41;
	pixel_a_3_1 = 47;
	pixel_b_3_1 = 255;
	pixel_a_3_2 = 252;
	pixel_b_3_2 = 34;
	pixel_a_3_3 = 220;
	pixel_b_3_3 = 20;
	#1 dummy = 1;
	fori = 1600;
	$display ("!!! Res=(%d) Expect=(%d)", out, fori);
	l = out;
	if (l != fori)
	begin
		$display ("!!! Error (%d, %d)!!!", fori, l);
	end
	#1 dummy = 1;
		end
endmodule

Pixel Block 1

8 bit	8 bit	8 bit	8 bit
8 bit	8 bit	8 bit	8 bit
8 bit	8 bit	8 bit	8 bit
8 bit	8 bit	8 bit	8 bit

Pixel Block 2

8 bit	8 bit	8 bit	8 bit
8 bit	8 bit	8 bit	8 bit
8 bit	8 bit	8 bit	8 bit
8 bit	8 bit	8 bit	8 bit

ABS SUB [-]
1

ABS SUB [-]
2

ABS SUB [-]
3

ABS SUB [-]
4

ABS SUB [-]
5

ABS SUB [-]
6

ABS SUB [-]
7

ABS SUB [-]
8

ABS SUB [-]
9

ABS SUB [-]
10

ABS SUB [-]
11

ABS SUB [-]
12

ABS SUB [-]
13

ABS SUB [-]
14

ABS SUB [-]
15

ABS SUB [-]
16

↓

SUM[+] 8 bit 1	SUM[+] 8 bit 2	SUM[+] 8 bit 3	SUM[+] 8 bit 4	SUM[+] 8 bit 5	SUM[+] 8 bit 6	SUM[+] 8 bit 7	SUM[+] 8 bit 8
↓	↓	↓	↓	↓	↓	↓	↓

SUM[+] 9 bit 1	SUM[+] 9 bit 2	SUM[+] 9 bit 3	SUM[+] 9 bit 4
↓	↓	↓	↓

SUM[+] 10 bit 1	SUM[+] 10 bit 2
↓	↓

SUM[+]
11 bit
1

↓