Генератор Verilog для позиционного синхронного вычислителя скалярного произведения

Разрядность выхода рассчитывается таким образом что бы операции над самым длинным вектором не выводили за границы диапазона.

Битность входа: 8
Битность выхода: 19

module sum_stage_1 (clk, a, b, out);
	input clk;
	input [7:0] a;
	input [7:0] b;
	output reg [15:0] out;
	
	wire sum_2_pow_0;
	wire [1:0] sum_2_pow_1;
	wire [1:0] sum_2_pow_2;
	wire [2:0] sum_2_pow_3;
	wire [2:0] sum_2_pow_4;
	wire [2:0] sum_2_pow_5;
	wire [2:0] sum_2_pow_6;
	wire [3:0] sum_2_pow_7;
	wire [2:0] sum_2_pow_8;
	wire [2:0] sum_2_pow_9;
	wire [2:0] sum_2_pow_10;
	wire [2:0] sum_2_pow_11;
	wire [1:0] sum_2_pow_12;
	wire [1:0] sum_2_pow_13;
	wire sum_2_pow_14;
	assign sum_2_pow_0 = a[0]*b[0]; // Max sum = 1
	assign sum_2_pow_1 = a[0]*b[1] + a[1]*b[0]; // Max sum = 2
	assign sum_2_pow_2 = a[0]*b[2] + a[1]*b[1] + a[2]*b[0]; // Max sum = 3
	assign sum_2_pow_3 = a[0]*b[3] + a[1]*b[2] + a[2]*b[1] + a[3]*b[0]; // Max sum = 4
	assign sum_2_pow_4 = a[0]*b[4] + a[1]*b[3] + a[2]*b[2] + a[3]*b[1] + a[4]*b[0]; // Max sum = 5
	assign sum_2_pow_5 = a[0]*b[5] + a[1]*b[4] + a[2]*b[3] + a[3]*b[2] + a[4]*b[1] + a[5]*b[0]; // Max sum = 6
	assign sum_2_pow_6 = a[0]*b[6] + a[1]*b[5] + a[2]*b[4] + a[3]*b[3] + a[4]*b[2] + a[5]*b[1] + a[6]*b[0]; // Max sum = 7
	assign sum_2_pow_7 = a[0]*b[7] + a[1]*b[6] + a[2]*b[5] + a[3]*b[4] + a[4]*b[3] + a[5]*b[2] + a[6]*b[1] + a[7]*b[0]; // Max sum = 8
	assign sum_2_pow_8 = a[1]*b[7] + a[2]*b[6] + a[3]*b[5] + a[4]*b[4] + a[5]*b[3] + a[6]*b[2] + a[7]*b[1]; // Max sum = 7
	assign sum_2_pow_9 = a[2]*b[7] + a[3]*b[6] + a[4]*b[5] + a[5]*b[4] + a[6]*b[3] + a[7]*b[2]; // Max sum = 6
	assign sum_2_pow_10 = a[3]*b[7] + a[4]*b[6] + a[5]*b[5] + a[6]*b[4] + a[7]*b[3]; // Max sum = 5
	assign sum_2_pow_11 = a[4]*b[7] + a[5]*b[6] + a[6]*b[5] + a[7]*b[4]; // Max sum = 4
	assign sum_2_pow_12 = a[5]*b[7] + a[6]*b[6] + a[7]*b[5]; // Max sum = 3
	assign sum_2_pow_13 = a[6]*b[7] + a[7]*b[6]; // Max sum = 2
	assign sum_2_pow_14 = a[7]*b[7]; // Max sum = 1

	reg [2:0] pyramid_level_1_pos_0; // Max val: 5
	reg [3:0] pyramid_level_1_pos_2; // Max val: 11
	reg [4:0] pyramid_level_1_pos_4; // Max val: 17
	reg [4:0] pyramid_level_1_pos_6; // Max val: 23
	reg [4:0] pyramid_level_1_pos_8; // Max val: 19
	reg [3:0] pyramid_level_1_pos_10; // Max val: 13
	reg [2:0] pyramid_level_1_pos_12; // Max val: 7
	reg [0:0] pyramid_level_1_pos_14; // Max val: 1
	reg [5:0] pyramid_level_2_pos_0; // Max val: 49
	reg [6:0] pyramid_level_2_pos_2; // Max val: 109
	reg [6:0] pyramid_level_2_pos_4; // Max val: 71
	reg [3:0] pyramid_level_2_pos_6; // Max val: 11
	reg [10:0] pyramid_level_3_pos_0; // Max val: 1793
	reg [7:0] pyramid_level_3_pos_2; // Max val: 247
	
	always @ (posedge clk)
	begin
		// Level 1
		pyramid_level_1_pos_0 <= sum_2_pow_0 + sum_2_pow_1 * 2; // Max val: 5
		pyramid_level_1_pos_2 <= sum_2_pow_2 + sum_2_pow_3 * 2; // Max val: 11
		pyramid_level_1_pos_4 <= sum_2_pow_4 + sum_2_pow_5 * 2; // Max val: 17
		pyramid_level_1_pos_6 <= sum_2_pow_6 + sum_2_pow_7 * 2; // Max val: 23
		pyramid_level_1_pos_8 <= sum_2_pow_8 + sum_2_pow_9 * 2; // Max val: 19
		pyramid_level_1_pos_10 <= sum_2_pow_10 + sum_2_pow_11 * 2; // Max val: 13
		pyramid_level_1_pos_12 <= sum_2_pow_12 + sum_2_pow_13 * 2; // Max val: 7
		pyramid_level_1_pos_14 <= sum_2_pow_14; // Max val: 1

		// Level 2
		pyramid_level_2_pos_0 <= pyramid_level_1_pos_0 + pyramid_level_1_pos_2 * 4; // Max val: 49
		pyramid_level_2_pos_2 <= pyramid_level_1_pos_4 + pyramid_level_1_pos_6 * 4; // Max val: 109
		pyramid_level_2_pos_4 <= pyramid_level_1_pos_8 + pyramid_level_1_pos_10 * 4; // Max val: 71
		pyramid_level_2_pos_6 <= pyramid_level_1_pos_12 + pyramid_level_1_pos_14 * 4; // Max val: 11

		// Level 3
		pyramid_level_3_pos_0 <= pyramid_level_2_pos_0 + pyramid_level_2_pos_2 * 16; // Max val: 1793
		pyramid_level_3_pos_2 <= pyramid_level_2_pos_4 + pyramid_level_2_pos_6 * 16; // Max val: 247

		// Level 4
		out <= pyramid_level_3_pos_0 + pyramid_level_3_pos_2 * 256; // Max val: 65025

	end
endmodule

module sum_stage_2 (clk, mult, c, out);
	input clk;
	input [15:0] mult;
	input [18:0] c;
	output reg [18:0] out;
	
	always @ (posedge clk)
	begin
		out <= mult + c;
	end
endmodule

module scalar_multiply
(
	input clk,
	input [7:0] a,
	input [7:0] b,
	output [18:0] out
);
	wire [15:0] mult;
	reg [18:0] old_res;
	sum_stage_1 mul_inst(clk, a, b, mult);
	sum_stage_2 sum_inst(clk, mult, old_res, out);
	
	initial begin
		old_res = 0;
	end
	
	always @ (out)
	begin
		old_res <= out;
	end
endmodule

module a_test_bench();
	reg clock;
	reg [7:0] a, b;
	wire [18:0] out;	
	
	integer expected = 0;
	integer dummy = 0;

	scalar_multiply s1 (clock, a, b, out);
	
	// Initialize all variables
	initial begin        
	$display ("Start!");
	clock = 1;  // initial value of clock
	a = 0;      // initial value of a
	b = 0;      // initial value of b
	
	#1 clock = 0;
	#1 clock = 0;
	#1 a = 27;
	#1 b = 87;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 0", out);
	#1 clock = 0;
	#1 a = 202;
	#1 b = 52;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 2349", out);
	#1 clock = 0;
	#1 a = 208;
	#1 b = 139;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 12853", out);
	#1 clock = 0;
	#1 a = 217;
	#1 b = 159;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 41765", out);
	#1 clock = 0;
	#1 a = 62;
	#1 b = 185;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 76268", out);
	#1 clock = 0;
	#1 a = 22;
	#1 b = 150;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 87738", out);
	#1 clock = 0;
	#1 a = 108;
	#1 b = 190;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 91038", out);
	#1 clock = 0;
	#1 a = 97;
	#1 b = 129;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 111558", out);
	#1 clock = 0;
	#1 a = 0;
	#1 b = 0;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 124071", out);
	#1 clock = 0;
	#1 a = 0;
	#1 b = 0;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 124071", out);
	#1 clock = 0;
	#1 a = 0;
	#1 b = 0;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 124071", out);
	#1 clock = 0;
	#1 a = 0;
	#1 b = 0;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expecting after 3 ticks: 124071", out);
	#1 clock = 0;
	#1 a = 0;
	#1 b = 0;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 124071", out);
	
	#1 clock = 0;
	$display ("Stop!");
	#1 clock = 1;
	end
endmodule

Описание:
- ускоренный конвеерезированный позиционный вычислитель скалярного произведения. Требуется log(bit)+1 тактов для получения промежуточных ответов на выходе конвеера. Суммарная латентность для получения окончательного результата N+log(bit)+1 (где N - длинна входного вектора, bit - размерность входных данных).