Генератор Verilog для прямого преобразователя в базис вида (2ⁿ-1, 2ⁿ+1, 2ⁿ⁺¹-1, 2ⁿ⁺¹+1)

Выберите n для формулы 2^n (от 3 до 43): 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Максимальное значение на входе:

Прямой преобразователь для базиса: (7, 9, 15, 17). Значение на входе [0;5355)
// Forward converter for basis {7, 9, 15, 17} // x1 = in%7, ... module forward_converter_3_5354 (in, x1, x2, y1, y2); input [12:0] in; output [2:0] x1; output [3:0] x2; output [3:0] y1; output [4:0] y2; data_mod_7_5354 d1(in, x1); data_mod_9_5354 d2(in, x2); data_mod_15_5354 d3(in, y1); data_mod_17_5354 d4(in, y2); endmodule module data_mod_7_5354 (in, out); input [12:0] in; output [2:0] out; wire [2:0] x0; wire [2:0] x1; wire [2:0] x2; wire [2:0] x3; wire x4; assign x0 = in[2:0]; assign x1 = in[5:3]; assign x2 = in[8:6]; assign x3 = in[11:9]; assign x4 = in[12]; wire [4:0] preout_7; assign preout_7 = x0 + x1 + x2 + x3 + x4 ; mod_7_29 mod1(preout_7, out); endmodule module mod_7_29 (in, out); input [4:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 0; 8: out = 1; 9: out = 2; 10: out = 3; 11: out = 4; 12: out = 5; 13: out = 6; 14: out = 0; 15: out = 1; 16: out = 2; 17: out = 3; 18: out = 4; 19: out = 5; 20: out = 6; 21: out = 0; 22: out = 1; 23: out = 2; 24: out = 3; 25: out = 4; 26: out = 5; 27: out = 6; 28: out = 0; 29: out = 1; default: out = 0; endcase end endmodule module data_mod_9_5354 (in, out); input [12:0] in; output [3:0] out; wire [2:0] x0; wire [2:0] x1; wire [2:0] x2; wire [2:0] x3; wire x4; assign x0 = in[2:0]; assign x1 = in[5:3]; assign x2 = in[8:6]; assign x3 = in[11:9]; assign x4 = in[12]; wire [5:0] preout_9; assign preout_9 = x0 + 4'd9 - x1 + x2 + 4'd9 - x3 + x4 + 0; mod_9_42 mod2(preout_9, out); endmodule module mod_9_42 (in, out); input [5:0] in; output reg [3:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 0; 10: out = 1; 11: out = 2; 12: out = 3; 13: out = 4; 14: out = 5; 15: out = 6; 16: out = 7; 17: out = 8; 18: out = 0; 19: out = 1; 20: out = 2; 21: out = 3; 22: out = 4; 23: out = 5; 24: out = 6; 25: out = 7; 26: out = 8; 27: out = 0; 28: out = 1; 29: out = 2; 30: out = 3; 31: out = 4; 32: out = 5; 33: out = 6; 34: out = 7; 35: out = 8; 36: out = 0; 37: out = 1; 38: out = 2; 39: out = 3; 40: out = 4; 41: out = 5; 42: out = 6; default: out = 0; endcase end endmodule module data_mod_15_5354 (in, out); input [12:0] in; output [3:0] out; wire [3:0] x0; wire [3:0] x1; wire [3:0] x2; wire x3; assign x0 = in[3:0]; assign x1 = in[7:4]; assign x2 = in[11:8]; assign x3 = in[12]; wire [5:0] preout_15; assign preout_15 = x0 + x1 + x2 + x3 ; mod_15_46 mod1(preout_15, out); endmodule module mod_15_46 (in, out); input [5:0] in; output reg [3:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 9; 10: out = 10; 11: out = 11; 12: out = 12; 13: out = 13; 14: out = 14; 15: out = 0; 16: out = 1; 17: out = 2; 18: out = 3; 19: out = 4; 20: out = 5; 21: out = 6; 22: out = 7; 23: out = 8; 24: out = 9; 25: out = 10; 26: out = 11; 27: out = 12; 28: out = 13; 29: out = 14; 30: out = 0; 31: out = 1; 32: out = 2; 33: out = 3; 34: out = 4; 35: out = 5; 36: out = 6; 37: out = 7; 38: out = 8; 39: out = 9; 40: out = 10; 41: out = 11; 42: out = 12; 43: out = 13; 44: out = 14; 45: out = 0; 46: out = 1; default: out = 0; endcase end endmodule module data_mod_17_5354 (in, out); input [12:0] in; output [4:0] out; wire [3:0] x0; wire [3:0] x1; wire [3:0] x2; wire x3; assign x0 = in[3:0]; assign x1 = in[7:4]; assign x2 = in[11:8]; assign x3 = in[12]; wire [6:0] preout_17; assign preout_17 = x0 + 5'd17 - x1 + x2 + 5'd17 - x3 + 0; mod_17_66 mod2(preout_17, out); endmodule module mod_17_66 (in, out); input [6:0] in; output reg [4:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 9; 10: out = 10; 11: out = 11; 12: out = 12; 13: out = 13; 14: out = 14; 15: out = 15; 16: out = 16; 17: out = 0; 18: out = 1; 19: out = 2; 20: out = 3; 21: out = 4; 22: out = 5; 23: out = 6; 24: out = 7; 25: out = 8; 26: out = 9; 27: out = 10; 28: out = 11; 29: out = 12; 30: out = 13; 31: out = 14; 32: out = 15; 33: out = 16; 34: out = 0; 35: out = 1; 36: out = 2; 37: out = 3; 38: out = 4; 39: out = 5; 40: out = 6; 41: out = 7; 42: out = 8; 43: out = 9; 44: out = 10; 45: out = 11; 46: out = 12; 47: out = 13; 48: out = 14; 49: out = 15; 50: out = 16; 51: out = 0; 52: out = 1; 53: out = 2; 54: out = 3; 55: out = 4; 56: out = 5; 57: out = 6; 58: out = 7; 59: out = 8; 60: out = 9; 61: out = 10; 62: out = 11; 63: out = 12; 64: out = 13; 65: out = 14; 66: out = 15; default: out = 0; endcase end endmodule module atest_bench(); reg [12:0] in; wire [2:0] x1; wire [3:0] x2; wire [3:0] y1; wire [4:0] y2; integer i, j, k, l, m, n, o, t; reg dummy; integer fori; forward_converter_3_5354 r1(in, x1, x2, y1, y2); initial begin for (fori = 0; fori < 13'd5355; fori = fori + 1) begin in = fori; #1 dummy = 1; l = fori%3'd7; m = fori%4'd9; n = fori%4'd15; o = fori%5'd17; $display ("!!! Input = (%d) Res = (%d, %d, %d %d) Expect = (%d, %d, %d %d)", fori, x1, x2, y1, y2, l, m, n, o); i = x1; j = x2; k = y1; t = y2; if (i != l || j != m || k != n || t != o) begin $display ("!!! Error (%d, %d, %d, %d, %d)!!!", fori, i, j, k, t); end #1 dummy = 1; end end endmodule

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