Генератор Verilog для бинарных умножителей на базе модулярного базиса 2ⁿ-1, 2ⁿ+1, 2ⁿ⁺¹-1, 2ⁿ⁺¹+1

Выберите битность входов умножителя (от 3 до 64): 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Выбранная битность: 3 (Максимальное значение на выходе: 64)
Степень n для базиса {2ⁿ-1, 2ⁿ+1, 2ⁿ⁺¹-1, 2ⁿ⁺¹+1}: 2 Покрывается интервал: [0; 315)
Базис: {2ⁿ-1, 2ⁿ+1, 2ⁿ⁺¹-1, 2ⁿ⁺¹+1} или [3, 5, 7, 9]

module mul_binary_3 (A, B, out); input [2:0] A; input [2:0] B; output [5:0] out; wire [1:0] A_x1; wire [2:0] A_x2; wire [2:0] A_y1; wire [3:0] A_y2; wire [1:0] B_x1; wire [2:0] B_x2; wire [2:0] B_y1; wire [3:0] B_y2; wire [1:0] RES_x1; wire [2:0] RES_x2; wire [2:0] RES_y1; wire [3:0] RES_y2; forward_converter fconv1(A, A_x1, A_x2, A_y1, A_y2); forward_converter fconv2(B, B_x1, B_x2, B_y1, B_y2); mul_channel_3 mulch_x1(A_x1, B_x1, RES_x1); mul_channel_5 mulch_x2(A_x2, B_x2, RES_x2); mul_channel_7 mulch_y1(A_y1, B_y1, RES_y1); mul_channel_9 mulch_y2(A_y2, B_y2, RES_y2); reverse_converter_3_5_7_9 revconv(RES_x1, RES_x2, RES_y1, RES_y2, out); endmodule // Forward converter for basis {3, 5, 7, 9} // x1 = in%3, ... module forward_converter (in, x1, x2, y1, y2); input [2:0] in; output [1:0] x1; output [2:0] x2; output [2:0] y1; output [3:0] y2; data_mod_3_7 d1(in, x1); data_mod_5_7 d2(in, x2); data_mod_7_7 d3(in, y1); data_mod_9_7 d4(in, y2); endmodule module data_mod_3_7 (in, out); input [2:0] in; output [1:0] out; wire [1:0] x0; wire x1; assign x0 = in[1:0]; assign x1 = in[2]; wire [2:0] preout_3; assign preout_3 = x0 + x1 ; mod_3_4 mod1(preout_3, out); endmodule module mod_3_4 (in, out); input [2:0] in; output reg [1:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 0; 4: out = 1; default: out = 0; endcase end endmodule module data_mod_5_7 (in, out); input [2:0] in; output [2:0] out; wire [1:0] x0; wire x1; assign x0 = in[1:0]; assign x1 = in[2]; wire [3:0] preout_5; assign preout_5 = x0 + 3'd5 - x1 + 0; mod_5_9 mod2(preout_5, out); endmodule module mod_5_9 (in, out); input [3:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 0; 6: out = 1; 7: out = 2; 8: out = 3; 9: out = 4; default: out = 0; endcase end endmodule module data_mod_7_7 (in, out); input [2:0] in; output [2:0] out; wire [2:0] x0; assign x0 = in[2:0]; wire [2:0] preout_7; assign preout_7 = x0 ; mod_7_7 mod1(preout_7, out); endmodule module mod_7_7 (in, out); input [2:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 0; default: out = 0; endcase end endmodule module data_mod_9_7 (in, out); input [2:0] in; output [3:0] out; wire [2:0] x0; assign x0 = in[2:0]; wire [3:0] preout_9; assign preout_9 = x0 + 0; mod_9_8 mod2(preout_9, out); endmodule module mod_9_8 (in, out); input [3:0] in; output reg [3:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; default: out = 0; endcase end endmodule // N = 2 Динамический диапазон: 315 >= 64 // Обратный конвертор для базиса: [3 5 7 9] module reverse_converter_3_5_7_9 (x1, x2, y1, y2, out); input [1:0] x1; input [2:0] x2; input [2:0] y1; input [3:0] y2; // CRT1 maximum output value: 14 [4 bit] wire [3:0] crt1; // CRT2 maximum output value: 62 [6 bit] wire [5:0] crt2; output [5:0] out; crt1_module crtinst1(x1, x2, crt1); crt2_module crtinst2(y1, y2, crt2); crt_final_module crtfinal(crt1, crt2, out); endmodule module crt1_module(x, y, out); // Range [0; 2] input [1:0] x; // Range [0; 4] input [2:0] y; output [3:0] out; // Range [0; 8] wire [3:0] a1; // Adding constant we guarantee postivie value assign a1 = 3'd6 + x - y; // Range [0; 6] // Note (a1[0] << 3) - can only be 0 or 2^1 wire [2:0] a2; assign a2 = (a1[0] << 1) + a1[2:1] + a1[3:3]; wire [1:0] a3; mod_3_6 mod(a2, a3); assign out = y + a3 + (a3 << 2); endmodule module mod_3_6 (in, out); input [2:0] in; output reg [1:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 0; 4: out = 1; 5: out = 2; 6: out = 0; default: out = 0; endcase end endmodule module crt2_module(x, y, out); // Range [0; 6] input [2:0] x; // Range [0; 8] input [3:0] y; output [5:0] out; // Range [0; 20] wire [4:0] a1; // Adding constant we guarantee postivie value assign a1 = 4'd14 + x - y; // Range [0; 12] // Note (a1[0] << 2) - can only be 0 or 2^2 wire [3:0] a2; assign a2 = (a1[0] << 2) + a1[3:1] + a1[4:4]; wire [2:0] a3; mod_7_12 mod(a2, a3); assign out = y + a3 + (a3 << 3); endmodule module mod_7_12 (in, out); input [3:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 0; 8: out = 1; 9: out = 2; 10: out = 3; 11: out = 4; 12: out = 5; default: out = 0; endcase end endmodule module crt_final_module(x, y, out); // Range [0; 14] input [3:0] x; // Range [0; 62] input [5:0] y; output [5:0] out; // Module used: 5 // Range [0; 89] wire [6:0] a1; // Note: constant a1 must be divisible by 5 and 3 because we give it to div_by_3 module assign a1 = 7'd75 + x - y; // Range [0; 30] wire [4:0] a2; div_3 d3(a1, a2); // Range [0; 4] wire [2:0] a3; mod_5_30 mod(a2, a3); assign out = y + (a3 << 6) - a3; endmodule module div_3(in, out); input [6:0] in; output [4:0] out; // Maximum value after multiplication 3827 wire [11:0] intermediate; assign intermediate = in*43; assign out = intermediate[11:7]; endmodule module mod_5_30 (in, out); input [4:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 0; 6: out = 1; 7: out = 2; 8: out = 3; 9: out = 4; 10: out = 0; 11: out = 1; 12: out = 2; 13: out = 3; 14: out = 4; 15: out = 0; 16: out = 1; 17: out = 2; 18: out = 3; 19: out = 4; 20: out = 0; 21: out = 1; 22: out = 2; 23: out = 3; 24: out = 4; 25: out = 0; 26: out = 1; 27: out = 2; 28: out = 3; 29: out = 4; 30: out = 0; default: out = 0; endcase end endmodule module mul_channel_5 (A, B, out); input [2:0] A; input [2:0] B; output [2:0] out; wire [1:0] invA; wire [1:0] invB; wire [1:0] nA_0; wire [2:0] P_0; wire [1:0] nA_1; wire [2:0] P_1; reg [3:0] P_ALL; assign invA[0] = ~A[0]; assign invA[1] = ~A[1]; assign invB[0] = ~B[0]; assign invB[1] = ~B[1]; assign nA_0[0] = A[0]; assign nA_0[1] = A[1]; assign nA_1[0] = ~A[1]; assign nA_1[1] = A[0]; assign P_0 = (B[0]*nA_0); assign P_1 = (B[1]*nA_1) + !B[1]*1'b1; mod_5_10 mod(P_ALL, out); always @(*) begin if ((A == 3'd4) && (B == 3'd4)) P_ALL <= 1; else if (A == 3'd4) begin P_ALL <= invB + 2; end else if (B == 3'd4) begin P_ALL <= invA + 2; end else begin P_ALL <= P_0 + P_1 + 4; end end endmodule module mod_5_10 (in, out); input [3:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 0; 6: out = 1; 7: out = 2; 8: out = 3; 9: out = 4; 10: out = 0; default: out = 0; endcase end endmodule module mul_channel_3 (a, b, out); // Умножитель input [1:0] a, b; wire [3:0] intermediate; output reg [1:0] out; assign intermediate = {a[1:0], b[1:0]}; always @ (intermediate) begin // we have small values so we can use table here case (intermediate) 4'b0000: out = 0; 4'b0001: out = 0; 4'b0010: out = 0; 4'b0100: out = 0; 4'b0101: out = 1; 4'b0110: out = 2; 4'b1000: out = 0; 4'b1001: out = 2; 4'b1010: out = 1; default: out = 0; endcase end endmodule module mul_channel_9 (A, B, out); input [3:0] A; input [3:0] B; output [3:0] out; wire [2:0] invA; wire [2:0] invB; wire [2:0] nA_0; wire [3:0] P_0; wire [2:0] nA_1; wire [3:0] P_1; wire [2:0] nA_2; wire [3:0] P_2; reg [4:0] P_ALL; assign invA[0] = ~A[0]; assign invA[1] = ~A[1]; assign invA[2] = ~A[2]; assign invB[0] = ~B[0]; assign invB[1] = ~B[1]; assign invB[2] = ~B[2]; assign nA_0[0] = A[0]; assign nA_0[1] = A[1]; assign nA_0[2] = A[2]; assign nA_1[0] = ~A[2]; assign nA_1[1] = A[0]; assign nA_1[2] = A[1]; assign nA_2[0] = ~A[1]; assign nA_2[1] = ~A[2]; assign nA_2[2] = A[0]; assign P_0 = (B[0]*nA_0); assign P_1 = (B[1]*nA_1) + !B[1]*1'b1; assign P_2 = (B[2]*nA_2) + !B[2]*2'b11; mod_9_26 mod(P_ALL, out); always @(*) begin if ((A == 4'd8) && (B == 4'd8)) P_ALL <= 1; else if (A == 4'd8) begin P_ALL <= invB + 2; end else if (B == 4'd8) begin P_ALL <= invA + 2; end else begin P_ALL <= P_0 + P_1 + P_2 + 5; end end endmodule module mod_9_26 (in, out); input [4:0] in; output reg [3:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 0; 10: out = 1; 11: out = 2; 12: out = 3; 13: out = 4; 14: out = 5; 15: out = 6; 16: out = 7; 17: out = 8; 18: out = 0; 19: out = 1; 20: out = 2; 21: out = 3; 22: out = 4; 23: out = 5; 24: out = 6; 25: out = 7; 26: out = 8; default: out = 0; endcase end endmodule module mul_channel_7 (a, b, out); // Умножитель input [2:0] a, b; wire [4:0] intermediate; output [2:0] out; wire [2:0] p0, p1, p2; // ФОРМИРОВАНИЕ ЧАСТИЧНЫХ ПРОИЗВЕДЕНИЙ assign p0 = a[2:0] * b[0]; assign p1 = {(a[1:0]*b[1]), a[2]*b[1]}; assign p2 = {(a[0]*b[2]), a[2:1]*b[2]}; assign intermediate = p0 + p1 + p2; mod_7_19 mod(intermediate, out); endmodule // Faster but more area module mod_7_19 (in, out); input [4:0] in; output reg [2:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 0; 8: out = 1; 9: out = 2; 10: out = 3; 11: out = 4; 12: out = 5; 13: out = 6; 14: out = 0; 15: out = 1; 16: out = 2; 17: out = 3; 18: out = 4; 19: out = 5; default: out = 0; endcase end endmodule module atest_bench(); wire [5:0] out; reg [2:0] in1; reg [2:0] in2; integer i, j, k, l, m, n; integer fori, forj, forz; reg dummy; mul_binary_3 r1(in1, in2, out); initial begin /* Full range */ for (fori = 0; fori < 8; fori = fori + 1) begin for (forj = 0; forj < 8; forj = forj + 1) begin in1 = fori; in2 = forj; #1 dummy = 1; l = fori*forj; $display ("!!! Input = (%d, %d) Res = (%d) Expect = (%d)", fori, forj, out, l); i = out; if (i != l) begin $display ("!!! Error (%d, %d, %d, %d)!!!", fori, forj, i, l); end #1 dummy = 1; end end end endmodule

Описание: Генератор обычного двоичного умножителя вида X = A*B, где у входов разрядность n бит, а у выхода 2*n бит. Умножение выполнено на базе модулярной арифметики и специального набора модулей вида {2ⁿ-1, 2ⁿ+1, 2ⁿ⁺¹-1, 2ⁿ⁺¹+1} (формирующих 4 параллельных канала).

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