Verilog generator for RNS-based multi-bit multipliers

Selected number of bits: 3 (Maximal output value: 64)
Value of power n for basis {2ⁿ-1, 2ⁿ, 2ⁿ+1}: 3 (Maximal value: 504)
Basis {2^n-1, 2^n, 2^n+1}: {2³-1, 2³, 2³+1} or [7, 8, 9]
module mul_binary_3 (A, B, out);
	input [2:0] A;
	input [2:0] B;
	output [5:0] out;
	wire [2:0] A_1;
	wire [2:0] A_2;
	wire [3:0] A_3;
	wire [2:0] B_1;
	wire [2:0] B_2;
	wire [3:0] B_3;
	wire [2:0] RES_1;
	wire [2:0] RES_2;
	wire [3:0] RES_3;
	
	forward_converter fconv1(A, A_3, A_2, A_1);
	forward_converter fconv2(B, B_3, B_2, B_1);
	
	mul_channel_2_pow_n_minus_1 mulch1(A_1, B_1, RES_1);
	mul_channel_2_pow_n mulch2(A_2, B_2, RES_2);
	mul_channel_2_pow_n_plus_1 mulch3(A_3, B_3, RES_3);
	
	reverse_converter revconv(RES_3, RES_2, RES_1, out);
	
endmodule
	
module forward_converter (x, x_mod9, x_mod8, x_mod7);
	input  [2:0] x;
	output [3:0] x_mod9;
	output [2:0] x_mod8;
	output [2:0] x_mod7;

	wire [2:0] x0;
	assign x0 = x[2:0];
	wire [2:0] x_prom_7;
	assign x_prom_7 = x0 ;
	mod_7_7 mod1(x_prom_7, x_mod7);
	wire [3:0] x_prom_9;
	assign x_prom_9 = x0 + 0;
	mod_9_8 mod2(x_prom_9, x_mod9);
	assign x_mod8 = x[2:0];
endmodule

module mod_7_7 (in, out);
	input [2:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 0;
		default: out = 0;
	endcase
	end
endmodule

module mod_9_8 (in, out);
	input [3:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 7;
		8: out = 8;
		default: out = 0;
	endcase
	end
endmodule

// {9 8 7}
module reverse_converter (x1, x2, x3, out);
	input [3:0] x1;
	input [2:0] x2;
	input [2:0] x3;
	wire [5:0] a1;
	wire [5:0] a2;
	wire [5:0] a3;
	wire [5:0] sum1;
	wire [5:0] sum2;
	wire [5:0] sum3;
	output [5:0] out;
		
	coef_a1 ca1(x1,a1);
	coef_a2 ca2(x2,a2);
	coef_a3 ca3(x3,a3);
	sum_modulo_63 sm1(a2, a3, sum1);
	sub_a1_x1 sm2(a1, x1, sum2);
	sum_modulo_63 sm3(sum1, sum2, sum3);
	
	assign out[0] = x2[0];
	assign out[1] = x2[1];
	assign out[2] = x2[2];
	
	assign out[3] = sum3[0];
	assign out[4] = sum3[1];
	assign out[5] = sum3[2];
	
endmodule

module coef_a3 (x3, a3);
	input [2:0] x3;
	output [5:0] a3;
	assign a3[5] = x3[0];
	assign a3[4] = x3[2];
	assign a3[3] = x3[1];
	assign a3[2] = x3[0];
	assign a3[1] = x3[2];
	assign a3[0] = x3[1];
endmodule

module coef_a2 (x2, a2);
	input [2:0] x2;
	output [5:0] a2;
	assign a2[5] = ~x2[2];
	assign a2[4] = ~x2[1];
	assign a2[3] = ~x2[0];
	assign a2[2] = 1;
	assign a2[1] = 1;
	assign a2[0] = 1;
endmodule

module coef_a1 (x1, a1);
	input [3:0] x1;
	output [5:0] a1;
	wire bx;
	
	assign bx = x1[3] ^ x1[0];
	assign a1[5] = bx;
	assign a1[4] = x1[2];
	assign a1[3] = x1[1];
	assign a1[2] = bx;
	assign a1[1] = x1[2];
	assign a1[0] = x1[1];
	
endmodule

// Sum modulo (2^6 - 1) = 63
module sum_modulo_63 (in1, in2, out);
	input [5:0] in1;
	input [5:0] in2;
	output reg [5:0] out;
	wire [6:0] data;
	wire [6:0] data2;
	assign data = in1 + in2;
	assign data2 = in1 + in2 + 1;
	always @(*)
	begin
		if (data2[6] == 1)
			out <= data2[5:0];
		else
			out <= data[5:0];
	end
endmodule

module sub_a1_x1 (a1, x1, out);
	input [5:0] a1;
	input [3:0] x1;
	output [5:0] out;
	
	assign out = a1 - x1;
	
endmodule

module mul_channel_2_pow_n_plus_1 (A, B, out);
	input [3:0] A;
	input [3:0] B;
	output [3:0] out;
	wire [2:0] invA;
	wire [2:0] invB;
	wire [2:0] nA_0; 
	wire [3:0] P_0;
	wire [2:0] nA_1; 
	wire [3:0] P_1;
	wire [2:0] nA_2; 
	wire [3:0] P_2;
	reg [4:0] P_ALL;
	
	assign invA[0] = ~A[0];	
	assign invA[1] = ~A[1];	
	assign invA[2] = ~A[2];
	
	assign invB[0] = ~B[0];	
	assign invB[1] = ~B[1];	
	assign invB[2] = ~B[2];

	assign nA_0[0] = A[0];
	assign nA_0[1] = A[1];
	assign nA_0[2] = A[2];
	assign nA_1[0] = ~A[2];
	assign nA_1[1] = A[0];
	assign nA_1[2] = A[1];
	assign nA_2[0] = ~A[1];
	assign nA_2[1] = ~A[2];
	assign nA_2[2] = A[0];

	assign P_0 = (B[0]*nA_0);
	assign P_1 = (B[1]*nA_1) + !B[1]*1'b1;
	assign P_2 = (B[2]*nA_2) + !B[2]*2'b11;

	mod_9_26 mod(P_ALL, out);
	
	always @(*)
	begin
		if ((A == 4'd8) && (B == 4'd8))
			P_ALL <= 1;
		else if (A == 4'd8)
		begin
			P_ALL <= invB + 2;
		end
		else if (B == 4'd8)
		begin
			P_ALL <= invA + 2;
		end
		else
		begin
			P_ALL <= P_0 + P_1 + P_2 + 5;
		end
	end
	
endmodule

module mod_9_26 (in, out);
	input [4:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 7;
		8: out = 8;
		9: out = 0;
		10: out = 1;
		11: out = 2;
		12: out = 3;
		13: out = 4;
		14: out = 5;
		15: out = 6;
		16: out = 7;
		17: out = 8;
		18: out = 0;
		19: out = 1;
		20: out = 2;
		21: out = 3;
		22: out = 4;
		23: out = 5;
		24: out = 6;
		25: out = 7;
		26: out = 8;
		default: out = 0;
	endcase
	end
endmodule

module mul_channel_2_pow_n_minus_1 (a, b, out); // Умножитель 
 
	input  [2:0]  a, b; 
	wire  [4:0]  intermediate; 
	output  [2:0]  out; 
 
	wire [2:0] p0, p1, p2; 

	// ФОРМИРОВАНИЕ ЧАСТИЧНЫХ ПРОИЗВЕДЕНИЙ 
 
	assign p0 = a[2:0] * b[0]; 
	assign p1 = {(a[1:0]*b[1]), a[2]*b[1]}; 
	assign p2 = {(a[0]*b[2]), a[2:1]*b[2]}; 
 
	assign intermediate = p0 + p1 + p2;
	mod_7_19 mod(intermediate, out); 

endmodule

// Faster but more area
module mod_7_19 (in, out);
	input [4:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 0;
		8: out = 1;
		9: out = 2;
		10: out = 3;
		11: out = 4;
		12: out = 5;
		13: out = 6;
		14: out = 0;
		15: out = 1;
		16: out = 2;
		17: out = 3;
		18: out = 4;
		19: out = 5;
		default: out = 0;
	endcase
	end
endmodule


module mul_channel_2_pow_n (A, B, out);
	input [2:0] A;
	input [2:0] B;
	output [2:0] out;
	wire [4:0] intermediate;
	wire [2:0] p0, p1, p2; 

	assign p0 = A[2:0] * B[0]; 
	assign p1 = (A[1:0] << 1) * B[1]; 
	assign p2 = (A[0] << 2) * B[2]; 
	assign intermediate = p0 + p1 + p2;
	assign out = intermediate[2:0];
endmodule

module atest_bench();
	wire [5:0] out;
	reg [2:0] in1;
	reg [2:0] in2;
			
	integer i, j, k, l, m, n;
	integer fori, forj, forz;
	reg dummy;
	
	mul_binary_3 r1(in1, in2, out);
	
	initial
	begin
	/* Full range */
	for (fori = 0; fori < 8; fori = fori + 1)
	begin
		for (forj = 0; forj < 8; forj = forj + 1)
		begin
			in1 = fori;
			in2 = forj;
			#1 dummy = 1;
			l = fori*forj;
			$display ("!!! Input = (%d, %d) Res = (%d) Expect = (%d)", fori, forj, out, l);
			i = out;
			if (i != l)
			begin
				$display ("!!! Error (%d, %d, %d, %d)!!!", fori, forj, i, l);
			end
			#1 dummy = 1;
		end
	end
	end
endmodule
Description: Generator of conventional binary multiplier, where input operands have n bit length and output has 2*n bit length. Multiplication is based on RNS arithmetic and special set of moduli {2^n-1, 2^n, 2^n+1} forming 3 parallel channels.