Verilog generator for RNS multiplier modulo 2^n-1

module mul_channel_2_pow_n_minus_1 (a, b, out); // Multiplier 
 
	input  [2:0]  a, b; 
	wire  [4:0]  intermediate; 
	output  [2:0]  out; 
 
	wire [2:0] p0, p1, p2; 

	// Form partial products

	assign p0 = a[2:0] * b[0]; 
	assign p1 = {(a[1:0]*b[1]), a[2]*b[1]}; 
	assign p2 = {(a[0]*b[2]), a[2:1]*b[2]}; 
 
	assign intermediate = p0 + p1 + p2;
	mod_7_19 mod(intermediate, out); 

endmodule

// Faster but more area
module mod_7_19 (in, out);
	input [4:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 0;
		8: out = 1;
		9: out = 2;
		10: out = 3;
		11: out = 4;
		12: out = 5;
		13: out = 6;
		14: out = 0;
		15: out = 1;
		16: out = 2;
		17: out = 3;
		18: out = 4;
		19: out = 5;
		default: out = 0;
	endcase
	end
endmodule

module atest_bench();
	wire [2:0] out;
	reg [2:0] in1;
	reg [2:0] in2;
			
	integer i, j, k, l, m, n;
	reg dummy;
	integer fori, forj, forz;
	
	mul_channel_2_pow_n_minus_1 r1(in1, in2, out);
	
	initial
	begin
	/* Full range */
	for (fori = 0; fori < 7; fori = fori + 1)
	begin
		for (forj = 0; forj < 7; forj = forj + 1)
		begin
			in1 = fori;
			in2 = forj;
			#1 dummy = 1;
			l = (fori*forj)%7;
			$display ("!!! Input = (%d, %d) Res = (%d) Expect = (%d)", fori, forj, out, l);
			i = out;
			if (i != l)
			begin
				$display ("!!! Error (%d, %d, %d, %d)!!!", fori, forj, i, l);
			end
			#1 dummy = 1;
		end
	end
	end
endmodule
Description: