Генератор Verilog для умножителя по модулю 2^n+1
Выберите n для формулы 2
n
(от 3 до 43):
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Использовать модулятор меньшей площади
// Faster but more area module mod_9_26 (in, out); input [4:0] in; output reg [3:0] out; always @ (in) begin // we have small max value so we can use table here case (in) 0: out = 0; 1: out = 1; 2: out = 2; 3: out = 3; 4: out = 4; 5: out = 5; 6: out = 6; 7: out = 7; 8: out = 8; 9: out = 0; 10: out = 1; 11: out = 2; 12: out = 3; 13: out = 4; 14: out = 5; 15: out = 6; 16: out = 7; 17: out = 8; 18: out = 0; 19: out = 1; 20: out = 2; 21: out = 3; 22: out = 4; 23: out = 5; 24: out = 6; 25: out = 7; 26: out = 8; default: out = 0; endcase end endmodule module mul_modulo_9 (A, B, out); input [3:0] A; input [3:0] B; output [3:0] out; wire [2:0] invA; wire [2:0] invB; wire [2:0] nA_0; wire [3:0] P_0; wire [2:0] nA_1; wire [3:0] P_1; wire [2:0] nA_2; wire [3:0] P_2; reg [4:0] P_ALL; assign invA[0] = ~A[0]; assign invA[1] = ~A[1]; assign invA[2] = ~A[2]; assign invB[0] = ~B[0]; assign invB[1] = ~B[1]; assign invB[2] = ~B[2]; assign nA_0[0] = A[0]; assign nA_0[1] = A[1]; assign nA_0[2] = A[2]; assign nA_1[0] = ~A[2]; assign nA_1[1] = A[0]; assign nA_1[2] = A[1]; assign nA_2[0] = ~A[1]; assign nA_2[1] = ~A[2]; assign nA_2[2] = A[0]; assign P_0 = (B[0]*nA_0); assign P_1 = (B[1]*nA_1) + !B[1]*1'b1; assign P_2 = (B[2]*nA_2) + !B[2]*2'b11; mod_9_26 mod(P_ALL, out); always @(*) begin if ((A == 4'd8) && (B == 4'd8)) P_ALL <= 1; else if (A == 4'd8) begin P_ALL <= invB + 2; end else if (B == 4'd8) begin P_ALL <= invA + 2; end else begin P_ALL <= P_0 + P_1 + P_2 + 5; end end endmodule module atest_bench(); wire [3:0] out; reg [3:0] in1; reg [3:0] in2; integer i, j, k, l, m, n; reg dummy; integer fori, forj, forz; mul_modulo_9 r1(in1, in2, out); initial begin /* Full range */ for (fori = 0; fori < 4'd9; fori = fori + 1) begin for (forj = 0; forj < 4'd9; forj = forj + 1) begin in1 = fori; in2 = forj; #1 dummy = 1; l = (fori*forj)%4'd9; $display ("!!! Input = (%d, %d) Res = (%d) Expect = (%d)", fori, forj, out, l); i = out; if (i != l) begin $display ("!!! Error (%d, %d, %d, %d)!!!", fori, forj, i, l); end #1 dummy = 1; end end end endmodule
Описание работы
: Efficient VLSI Implementation of Modulo 2
n
+1 Addition and Multiplication (1999, Reto Zimmermann)
На главную