Генератор Verilog для умножителя по модулю 2^n

module mul_channel_2_pow_n (A, B, out);
	input [2:0] A;
	input [2:0] B;
	output [2:0] out;
	wire [4:0] intermediate;
	wire [2:0] p0, p1, p2; 

	assign p0 = A[2:0] * B[0]; 
	assign p1 = (A[1:0] << 1) * B[1]; 
	assign p2 = (A[0] << 2) * B[2]; 
	assign intermediate = p0 + p1 + p2;
	assign out = intermediate[2:0];
endmodule

module atest_bench();
	wire [2:0] out;
	reg [2:0] in1;
	reg [2:0] in2;
			
	integer i, j, k, l, m, n;
	reg dummy;
	integer fori, forj, forz;
	
	mul_channel_2_pow_n r1(in1, in2, out);
	
	initial
	begin
	/* Full range */
	for (fori = 0; fori < 4'd8; fori = fori + 1)
	begin
		for (forj = 0; forj < 4'd8; forj = forj + 1)
		begin
			in1 = fori;
			in2 = forj;
			#1 dummy = 1;
			l = (fori*forj)%4'd8;
			$display ("!!! Input = (%d, %d) Res = (%d) Expect = (%d)", fori, forj, out, l);
			i = out;
			if (i != l)
			begin
				$display ("!!! Error (%d, %d, %d, %d)!!!", fori, forj, i, l);
			end
			#1 dummy = 1;
		end
	end
	end
endmodule

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