Генератор Verilog для КИХ-фильтров (простой метод)
Выберите размерность чисел (от 4 до 24 бит):
4
5
6
7
8
9
10
11
12
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14
15
16
17
18
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20
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24
Выберите длину вектора (от 4 до 1024):
4
8
16
32
64
128
256
512
1024
Выдавать округленное значение до размерности входа:
Схема с конвеерезированным сумматором:
module fir_filter_8_bit_4_points (clock, reset, enable, data, out); input clock; input reset; input enable; input [7:0] data; output [17:0] out; wire [17:0] sum; reg [7:0] points [0:3]; reg counter; wire [7:0] stored [0:3]; assign stored[0] = 243; assign stored[1] = 100; assign stored[2] = 216; assign stored[3] = 104; assign out = sum; always @ (posedge clock) begin if (reset == 1'b1) begin points[0] = 0; points[1] = 0; points[2] = 0; points[3] = 0; end else if (enable == 1'b1) begin points[3] = points[2]; points[2] = points[1]; points[1] = points[0]; points[0] = data; end end assign sum = points[0]*stored[0] + points[1]*stored[1] + points[2]*stored[2] + points[3]*stored[3] ; endmodule module a_test_bench(); reg clock, reset, enable; reg [7:0] data; wire [17:0] out; integer expected = 0; fir_filter_8_bit_4_points ffilt (clock, reset, enable, data, out); // Initialize all variables initial begin $display ("time\t clk reset enable data out expected"); $monitor ("%g\t %b %b %b %d %d %d", $time, clock, reset, enable, data, out, expected); clock = 1; // initial value of clock reset = 0; // initial value of reset enable = 0; // initial value of enable data = 0; // initial value of data #5 reset = 1; // Assert the reset #10 reset = 0; // De-assert the reset #10 enable = 1; // Assert enable #10 data = 160; #10 data = 218; #10 data = 55; #10 data = 20; #10 data = 0; #10 data = 0; #10 data = 0; #10 data = 0; #100 enable = 0; // De-assert enable #5 $finish; // Terminate simulation end // Clock generator always begin #5 clock = ~clock; // Toggle clock every 5 ticks end endmodule
Описание
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