Генератор Verilog для позиционного синхронного MAC Unit

Разрядность выхода рассчитывается таким образом что бы операции над самым длинным вектором не выводили за границы диапазона.

Битность входа: 8
Битность выхода: 19

module mac_unit
(
	input clk, clr, en, sload,
	input [7:0] a,
	input [7:0] b,
	output reg [18:0] out
);
	reg [7:0] a_reg, b_reg;
	reg sload_reg;
	reg [18:0] old_res;
	wire [15:0] mult;

	assign mult = a_reg * b_reg;

	always @ (out or sload_reg)
	begin
		if (sload_reg)
			old_res <= 0;
		else
			old_res <= out;
	end

	// Clear or update data, as appropriate
	always @ (posedge clk or posedge clr)
	begin
		if (clr)
		begin
			a_reg <= 0;
			b_reg <= 0;
			sload_reg <= 0;
			out <= 0;
		end
		else if (en)
		begin
			a_reg <= a;
			b_reg <= b;
			sload_reg <= sload;
			out <= old_res + mult;
		end
	end
endmodule

module a_test_bench();
	reg clock, clear, enable, sload;
	reg [7:0] a, b;
	wire [18:0] out;	
	
	integer expected = 0;
	integer dummy = 0;

	mac_unit macunit (clock, clear, enable, sload, a, b, out);
	
	// Initialize all variables
	initial begin        
	$display ("Start!");
	clock = 1;  // initial value of clock
	clear = 0;  // initial value of clear
	enable = 0; // initial value of enable
	sload = 0;  // initial value of sload
	a = 0;      // initial value of a
	b = 0;      // initial value of b
	
	#1 clock = 0;
	#1 clear = 1;  // Assert the reset
	#1 clock = 1;
	#1 clock = 0;
	#1 clear = 0;  // De-assert the reset
	#1 clock = 1;
	#1 clock = 0;
	#1 enable = 1; // Assert enable
	#1 clock = 1;
	#1 clock = 0;
	#1 sload = 0; // Assert sload
	#1 clock = 1;
	
	#1 clock = 0;
	#1 a = 132;
	#1 b = 195;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 0", out);
	#1 clock = 0;
	#1 a = 228;
	#1 b = 254;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 25740", out);
	#1 clock = 0;
	#1 a = 254;
	#1 b = 200;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 83652", out);
	#1 clock = 0;
	#1 a = 62;
	#1 b = 182;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 134452", out);
	#1 clock = 0;
	#1 a = 223;
	#1 b = 80;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 145736", out);
	#1 clock = 0;
	#1 a = 253;
	#1 b = 59;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 163576", out);
	#1 clock = 0;
	#1 a = 21;
	#1 b = 43;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 178503", out);
	#1 clock = 0;
	#1 a = 222;
	#1 b = 114;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 179406", out);
	#1 clock = 0;
	#1 a = 0;
	#1 b = 0;
	#1 clock = 1;
	#1 dummy = 1;
	$display ("%d Expected: 204714", out);
	
	#1 clock = 0;
	$display ("Stop!");
	#100 enable = 0; // De-assert enable
	#1 clock = 1;
	end
endmodule

Описание:
- дефолтный позиционный MAC-Unit (умножение с накоплением).