Генератор Verilog для вычисления скалярного произведения на базе модулярной арифметики

Разрядность выхода рассчитывается таким образом что бы операции над самым длинным вектором не выводили за границы диапазона.
Битность входа: 8 Максимальное значение на входе: 255
Битность выхода: 18 Максимальное значение на выходе: 260100
Набор модулей: 3 5 7 11 13 17 19
Покрываемый диапазон: 4849845
module scalar_multiply
(
	input clk,
	input reset,
	input [7:0] a,
	input [7:0] b,
	output [1:0] out_3, 
	output [2:0] out_5, 
	output [2:0] out_7, 
	output [3:0] out_11, 
	output [3:0] out_13, 
	output [4:0] out_17, 
	output [4:0] out_19
);
	wire [1:0] ff_a_3;
	wire [1:0] ff_b_3;
	wire [1:0] mul_out_3;
	wire [2:0] ff_a_5;
	wire [2:0] ff_b_5;
	wire [2:0] mul_out_5;
	wire [2:0] ff_a_7;
	wire [2:0] ff_b_7;
	wire [2:0] mul_out_7;
	wire [3:0] ff_a_11;
	wire [3:0] ff_b_11;
	wire [3:0] mul_out_11;
	wire [3:0] ff_a_13;
	wire [3:0] ff_b_13;
	wire [3:0] mul_out_13;
	wire [4:0] ff_a_17;
	wire [4:0] ff_b_17;
	wire [4:0] mul_out_17;
	wire [4:0] ff_a_19;
	wire [4:0] ff_b_19;
	wire [4:0] mul_out_19;
	reg [1:0] old_res_3;
	reg [2:0] old_res_5;
	reg [2:0] old_res_7;
	reg [3:0] old_res_11;
	reg [3:0] old_res_13;
	reg [4:0] old_res_17;
	reg [4:0] old_res_19;
	forward_conv ffa (clk, reset, ff_a_3, ff_a_5, ff_a_7, ff_a_11, ff_a_13, ff_a_17, ff_a_19, a);
	forward_conv ffb (clk, reset, ff_b_3, ff_b_5, ff_b_7, ff_b_11, ff_b_13, ff_b_17, ff_b_19, b);
	multiplication_mod_3 mm3 (clk, reset, ff_a_3, ff_b_3, mul_out_3);
	multiplication_mod_5 mm5 (clk, reset, ff_a_5, ff_b_5, mul_out_5);
	multiplication_mod_7 mm7 (clk, reset, ff_a_7, ff_b_7, mul_out_7);
	multiplication_mod_11 mm11 (clk, reset, ff_a_11, ff_b_11, mul_out_11);
	multiplication_mod_13 mm13 (clk, reset, ff_a_13, ff_b_13, mul_out_13);
	multiplication_mod_17 mm17 (clk, reset, ff_a_17, ff_b_17, mul_out_17);
	multiplication_mod_19 mm19 (clk, reset, ff_a_19, ff_b_19, mul_out_19);
	sum_modulo_3 sum3 (clk, reset, mul_out_3, old_res_3, out_3);
	sum_modulo_5 sum5 (clk, reset, mul_out_5, old_res_5, out_5);
	sum_modulo_7 sum7 (clk, reset, mul_out_7, old_res_7, out_7);
	sum_modulo_11 sum11 (clk, reset, mul_out_11, old_res_11, out_11);
	sum_modulo_13 sum13 (clk, reset, mul_out_13, old_res_13, out_13);
	sum_modulo_17 sum17 (clk, reset, mul_out_17, old_res_17, out_17);
	sum_modulo_19 sum19 (clk, reset, mul_out_19, old_res_19, out_19);
	always @ (*) begin
		if (reset == 1'b1) begin
			old_res_3 <= 0;
			old_res_5 <= 0;
			old_res_7 <= 0;
			old_res_11 <= 0;
			old_res_13 <= 0;
			old_res_17 <= 0;
			old_res_19 <= 0;
		end
		else begin
			old_res_3 <= out_3;
			old_res_5 <= out_5;
			old_res_7 <= out_7;
			old_res_11 <= out_11;
			old_res_13 <= out_13;
			old_res_17 <= out_17;
			old_res_19 <= out_19;
		end
	end
endmodule

module forward_conv (clk, reset, out0, out1, out2, out3, out4, out5, out6, in);
	input clk; // clock
	input reset;
	output [1:0] out0; // Module: 3
	output [2:0] out1; // Module: 5
	output [2:0] out2; // Module: 7
	output [3:0] out3; // Module: 11
	output [3:0] out4; // Module: 13
	output [4:0] out5; // Module: 17
	output [4:0] out6; // Module: 19
	wire [3:0] sum0; // Maxval: 12
	wire [4:0] sum1; // Maxval: 20
	wire [4:0] sum2; // Maxval: 17
	wire [5:0] sum3; // Maxval: 46
	wire [5:0] sum4; // Maxval: 47
	wire [6:0] sum5; // Maxval: 68
	wire [6:0] sum6; // Maxval: 65
	input [7:0] in; // Max value: 255

	sum_stage_3 inst_sum_3(clk, reset, in, sum0);
	correction_stage_3 inst_corr_3(clk, reset, sum0, out0);
	sum_stage_5 inst_sum_5(clk, reset, in, sum1);
	correction_stage_5 inst_corr_5(clk, reset, sum1, out1);
	sum_stage_7 inst_sum_7(clk, reset, in, sum2);
	correction_stage_7 inst_corr_7(clk, reset, sum2, out2);
	sum_stage_11 inst_sum_11(clk, reset, in, sum3);
	correction_stage_11 inst_corr_11(clk, reset, sum3, out3);
	sum_stage_13 inst_sum_13(clk, reset, in, sum4);
	correction_stage_13 inst_corr_13(clk, reset, sum4, out4);
	sum_stage_17 inst_sum_17(clk, reset, in, sum5);
	correction_stage_17 inst_corr_17(clk, reset, sum5, out5);
	sum_stage_19 inst_sum_19(clk, reset, in, sum6);
	correction_stage_19 inst_corr_19(clk, reset, sum6, out6);
endmodule

module sum_stage_3 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [3:0] out; // Max value: 12
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[1:0] + in[2] + 2*in[3] + in[4] + 2*in[5] + in[6] + 2*in[7];
		end
	end
endmodule

module correction_stage_3 (clk, reset, in, out);
	input clk;
	input reset;
	input [3:0] in; // Max value: 12
	output reg [1:0] out; // Max value: 2
	wire [1:0] inter; // Max value: 2
	mod_3_12 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_3_12 (in, out);
	input [3:0] in;
	output reg [1:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out <= 0;
		1: out <= 1;
		2: out <= 2;
		3: out <= 0;
		4: out <= 1;
		5: out <= 2;
		6: out <= 0;
		7: out <= 1;
		8: out <= 2;
		9: out <= 0;
		10: out <= 1;
		11: out <= 2;
		12: out <= 0;
		default: out <= 0;
	endcase
	end
endmodule

module sum_stage_5 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [4:0] out; // Max value: 20
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[2:0] + 3*in[3] + in[4] + 2*in[5] + 4*in[6] + 3*in[7];
		end
	end
endmodule

module correction_stage_5 (clk, reset, in, out);
	input clk;
	input reset;
	input [4:0] in; // Max value: 20
	output reg [2:0] out; // Max value: 4
	wire [2:0] inter; // Max value: 4
	mod_5_20 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_5_20 (in, out);
	input [4:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd5)
		begin
			out <= in;
		end
		else if (in < 4'd10)
		begin
			out <= in - 3'd5;
		end
		else if (in < 4'd15)
		begin
			out <= in - 4'd10;
		end
		else if (in < 5'd20)
		begin
			out <= in - 4'd15;
		end
		else
		begin
			out <= in - 5'd20;
		end
	end
endmodule

module sum_stage_7 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [4:0] out; // Max value: 17
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[2:0] + in[3] + 2*in[4] + 4*in[5] + in[6] + 2*in[7];
		end
	end
endmodule

module correction_stage_7 (clk, reset, in, out);
	input clk;
	input reset;
	input [4:0] in; // Max value: 17
	output reg [2:0] out; // Max value: 6
	wire [2:0] inter; // Max value: 6
	mod_7_17 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_7_17 (in, out);
	input [4:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out <= 0;
		1: out <= 1;
		2: out <= 2;
		3: out <= 3;
		4: out <= 4;
		5: out <= 5;
		6: out <= 6;
		7: out <= 0;
		8: out <= 1;
		9: out <= 2;
		10: out <= 3;
		11: out <= 4;
		12: out <= 5;
		13: out <= 6;
		14: out <= 0;
		15: out <= 1;
		16: out <= 2;
		17: out <= 3;
		default: out <= 0;
	endcase
	end
endmodule

module sum_stage_11 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [5:0] out; // Max value: 46
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[3:0] + 5*in[4] + 10*in[5] + 9*in[6] + 7*in[7];
		end
	end
endmodule

module correction_stage_11 (clk, reset, in, out);
	input clk;
	input reset;
	input [5:0] in; // Max value: 46
	output reg [3:0] out; // Max value: 10
	wire [3:0] inter; // Max value: 10
	mod_11_46 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_11_46 (in, out);
	input [5:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
		if (in < 4'd11)
		begin
			out <= in;
		end
		else if (in < 5'd22)
		begin
			out <= in - 4'd11;
		end
		else if (in < 6'd33)
		begin
			out <= in - 5'd22;
		end
		else if (in < 6'd44)
		begin
			out <= in - 6'd33;
		end
		else
		begin
			out <= in - 6'd44;
		end
	end
endmodule

module sum_stage_13 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [5:0] out; // Max value: 47
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[3:0] + 3*in[4] + 6*in[5] + 12*in[6] + 11*in[7];
		end
	end
endmodule

module correction_stage_13 (clk, reset, in, out);
	input clk;
	input reset;
	input [5:0] in; // Max value: 47
	output reg [3:0] out; // Max value: 12
	wire [3:0] inter; // Max value: 12
	mod_13_47 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_13_47 (in, out);
	input [5:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
		if (in < 4'd13)
		begin
			out <= in;
		end
		else if (in < 5'd26)
		begin
			out <= in - 4'd13;
		end
		else if (in < 6'd39)
		begin
			out <= in - 5'd26;
		end
		else
		begin
			out <= in - 6'd39;
		end
	end
endmodule

module sum_stage_17 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [6:0] out; // Max value: 68
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[4:0] + 15*in[5] + 13*in[6] + 9*in[7];
		end
	end
endmodule

module correction_stage_17 (clk, reset, in, out);
	input clk;
	input reset;
	input [6:0] in; // Max value: 68
	output reg [4:0] out; // Max value: 16
	wire [4:0] inter; // Max value: 16
	mod_17_68 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_17_68 (in, out);
	input [6:0] in;
	output reg [4:0] out;
	always @ (in)
	begin
		if (in < 5'd17)
		begin
			out <= in;
		end
		else if (in < 6'd34)
		begin
			out <= in - 5'd17;
		end
		else if (in < 6'd51)
		begin
			out <= in - 6'd34;
		end
		else if (in < 7'd68)
		begin
			out <= in - 6'd51;
		end
		else
		begin
			out <= in - 7'd68;
		end
	end
endmodule

module sum_stage_19 (clk, reset, in, out);
	input clk;
	input reset;
	input [7:0] in; // Max value: 255
	output reg [6:0] out; // Max value: 65
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= in[4:0] + 13*in[5] + 7*in[6] + 14*in[7];
		end
	end
endmodule

module correction_stage_19 (clk, reset, in, out);
	input clk;
	input reset;
	input [6:0] in; // Max value: 65
	output reg [4:0] out; // Max value: 18
	wire [4:0] inter; // Max value: 18
	mod_19_65 inst(in, inter);
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inter;
		end
	end
endmodule

module mod_19_65 (in, out);
	input [6:0] in;
	output reg [4:0] out;
	always @ (in)
	begin
		if (in < 5'd19)
		begin
			out <= in;
		end
		else if (in < 6'd38)
		begin
			out <= in - 5'd19;
		end
		else if (in < 6'd57)
		begin
			out <= in - 6'd38;
		end
		else
		begin
			out <= in - 6'd57;
		end
	end
endmodule

module singular (clk, reset, inp, out);
	input clk;
	input reset;
	input inp;
	output reg out;
				
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else begin
			out <= inp;
		end
	end
endmodule

module multiplication_mod_3(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [1:0] inp1;
	input [1:0] inp2;
	output [1:0] out;
	wire [1:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	lut_input_3 lut1(clk, reset, inp1, w_1_0);
	lut_input_3 lut2(clk, reset, inp2, w_2_0);
	sum_modulo_2 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	lut_output_3 lut3(clk, reset, wout_0, out_pre);
	singularity_pass_3 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_3 (in_singular, in2, out);
	input in_singular;
	input [1:0] in2;
	output reg [1:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_3 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [1:0] inp1;
	input [1:0] inp2;
	input [1:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [1:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_3 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module sum_modulo_2(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 2)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 2;
		end
	end
endmodule

module lut_output_3(clk, reset, inp0, out);
	input clk;
	input reset;
	output reg [1:0] out;
	input [1:0] inp0;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 1)
		begin
			out <= 2;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_3(clk, reset, inp, out0);
	input clk;
	input reset;
	input [1:0] inp;
	output reg [1:0] out0;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
		end
		2:
		begin
			out0 <= 1;
		end
		default:
		begin
			out0 <= 0;
		end
		endcase
		end
	end
endmodule

module multiplication_mod_5(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	output [2:0] out;
	wire [2:0] out_pre;
	wire [2:0] w_1_0;
	wire [2:0] w_2_0;
	wire [2:0] wout_0;
	lut_input_5 lut1(clk, reset, inp1, w_1_0);
	lut_input_5 lut2(clk, reset, inp2, w_2_0);
	sum_modulo_4 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	lut_output_5 lut3(clk, reset, wout_0, out_pre);
	singularity_pass_5 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_5 (in_singular, in2, out);
	input in_singular;
	input [2:0] in2;
	output reg [2:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_5 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	input [2:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [2:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_5 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module sum_modulo_4(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	output reg [2:0] out;
	wire [3:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 4)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 4;
		end
	end
endmodule

module lut_output_5(clk, reset, inp0, out);
	input clk;
	input reset;
	output reg [2:0] out;
	input [2:0] inp0;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 1)
		begin
			out <= 2;
		end
		else if (inp0 == 3)
		begin
			out <= 3;
		end
		else if (inp0 == 2)
		begin
			out <= 4;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_5(clk, reset, inp, out0);
	input clk;
	input reset;
	input [2:0] inp;
	output reg [2:0] out0;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
		end
		2:
		begin
			out0 <= 1;
		end
		3:
		begin
			out0 <= 3;
		end
		4:
		begin
			out0 <= 2;
		end
		default:
		begin
			out0 <= 0;
		end
		endcase
		end
	end
endmodule

module multiplication_mod_7(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	output [2:0] out;
	wire [2:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	wire [1:0] w_1_1;
	wire [1:0] w_2_1;
	wire [1:0] wout_1;
	lut_input_7 lut1(clk, reset, inp1, w_1_0, w_1_1);
	lut_input_7 lut2(clk, reset, inp2, w_2_0, w_2_1);
	sum_modulo_2 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	sum_modulo_3 sm1(clk, reset, w_1_1, w_2_1, wout_1);
	lut_output_7 lut3(clk, reset, wout_0, wout_1, out_pre);
	singularity_pass_7 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_7 (in_singular, in2, out);
	input in_singular;
	input [2:0] in2;
	output reg [2:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_7 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	input [2:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [2:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_7 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module sum_modulo_3(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 3)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 3;
		end
	end
endmodule

module lut_output_7(clk, reset, inp0, inp1, out);
	input clk;
	input reset;
	output reg [2:0] out;
	input [1:0] inp0;
	input [1:0] inp1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0 && inp1 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 0 && inp1 == 2)
		begin
			out <= 2;
		end
		else if (inp0 == 1 && inp1 == 1)
		begin
			out <= 3;
		end
		else if (inp0 == 0 && inp1 == 1)
		begin
			out <= 4;
		end
		else if (inp0 == 1 && inp1 == 2)
		begin
			out <= 5;
		end
		else if (inp0 == 1 && inp1 == 0)
		begin
			out <= 6;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_7(clk, reset, inp, out0, out1);
	input clk;
	input reset;
	input [2:0] inp;
	output reg [1:0] out0;
	output reg [1:0] out1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
			out1 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		2:
		begin
			out0 <= 0;
			out1 <= 2;
		end
		3:
		begin
			out0 <= 1;
			out1 <= 1;
		end
		4:
		begin
			out0 <= 0;
			out1 <= 1;
		end
		5:
		begin
			out0 <= 1;
			out1 <= 2;
		end
		6:
		begin
			out0 <= 1;
			out1 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		endcase
		end
	end
endmodule

module multiplication_mod_11(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	output [3:0] out;
	wire [3:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	wire [2:0] w_1_1;
	wire [2:0] w_2_1;
	wire [2:0] wout_1;
	lut_input_11 lut1(clk, reset, inp1, w_1_0, w_1_1);
	lut_input_11 lut2(clk, reset, inp2, w_2_0, w_2_1);
	sum_modulo_2 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	sum_modulo_5 sm1(clk, reset, w_1_1, w_2_1, wout_1);
	lut_output_11 lut3(clk, reset, wout_0, wout_1, out_pre);
	singularity_pass_11 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_11 (in_singular, in2, out);
	input in_singular;
	input [3:0] in2;
	output reg [3:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_11 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	input [3:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [3:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_11 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module sum_modulo_5(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	output reg [2:0] out;
	wire [3:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 5)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 5;
		end
	end
endmodule

module lut_output_11(clk, reset, inp0, inp1, out);
	input clk;
	input reset;
	output reg [3:0] out;
	input [1:0] inp0;
	input [2:0] inp1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0 && inp1 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 1 && inp1 == 1)
		begin
			out <= 2;
		end
		else if (inp0 == 0 && inp1 == 3)
		begin
			out <= 3;
		end
		else if (inp0 == 0 && inp1 == 2)
		begin
			out <= 4;
		end
		else if (inp0 == 0 && inp1 == 4)
		begin
			out <= 5;
		end
		else if (inp0 == 1 && inp1 == 4)
		begin
			out <= 6;
		end
		else if (inp0 == 1 && inp1 == 2)
		begin
			out <= 7;
		end
		else if (inp0 == 1 && inp1 == 3)
		begin
			out <= 8;
		end
		else if (inp0 == 0 && inp1 == 1)
		begin
			out <= 9;
		end
		else if (inp0 == 1 && inp1 == 0)
		begin
			out <= 10;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_11(clk, reset, inp, out0, out1);
	input clk;
	input reset;
	input [3:0] inp;
	output reg [1:0] out0;
	output reg [2:0] out1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
			out1 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		2:
		begin
			out0 <= 1;
			out1 <= 1;
		end
		3:
		begin
			out0 <= 0;
			out1 <= 3;
		end
		4:
		begin
			out0 <= 0;
			out1 <= 2;
		end
		5:
		begin
			out0 <= 0;
			out1 <= 4;
		end
		6:
		begin
			out0 <= 1;
			out1 <= 4;
		end
		7:
		begin
			out0 <= 1;
			out1 <= 2;
		end
		8:
		begin
			out0 <= 1;
			out1 <= 3;
		end
		9:
		begin
			out0 <= 0;
			out1 <= 1;
		end
		10:
		begin
			out0 <= 1;
			out1 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		endcase
		end
	end
endmodule

module multiplication_mod_13(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	output [3:0] out;
	wire [3:0] out_pre;
	wire [2:0] w_1_0;
	wire [2:0] w_2_0;
	wire [2:0] wout_0;
	wire [1:0] w_1_1;
	wire [1:0] w_2_1;
	wire [1:0] wout_1;
	lut_input_13 lut1(clk, reset, inp1, w_1_0, w_1_1);
	lut_input_13 lut2(clk, reset, inp2, w_2_0, w_2_1);
	sum_modulo_4 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	sum_modulo_3 sm1(clk, reset, w_1_1, w_2_1, wout_1);
	lut_output_13 lut3(clk, reset, wout_0, wout_1, out_pre);
	singularity_pass_13 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_13 (in_singular, in2, out);
	input in_singular;
	input [3:0] in2;
	output reg [3:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_13 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	input [3:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [3:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_13 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module lut_output_13(clk, reset, inp0, inp1, out);
	input clk;
	input reset;
	output reg [3:0] out;
	input [2:0] inp0;
	input [1:0] inp1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0 && inp1 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 1 && inp1 == 1)
		begin
			out <= 2;
		end
		else if (inp0 == 0 && inp1 == 1)
		begin
			out <= 3;
		end
		else if (inp0 == 2 && inp1 == 2)
		begin
			out <= 4;
		end
		else if (inp0 == 1 && inp1 == 0)
		begin
			out <= 5;
		end
		else if (inp0 == 1 && inp1 == 2)
		begin
			out <= 6;
		end
		else if (inp0 == 3 && inp1 == 2)
		begin
			out <= 7;
		end
		else if (inp0 == 3 && inp1 == 0)
		begin
			out <= 8;
		end
		else if (inp0 == 0 && inp1 == 2)
		begin
			out <= 9;
		end
		else if (inp0 == 2 && inp1 == 1)
		begin
			out <= 10;
		end
		else if (inp0 == 3 && inp1 == 1)
		begin
			out <= 11;
		end
		else if (inp0 == 2 && inp1 == 0)
		begin
			out <= 12;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_13(clk, reset, inp, out0, out1);
	input clk;
	input reset;
	input [3:0] inp;
	output reg [2:0] out0;
	output reg [1:0] out1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
			out1 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		2:
		begin
			out0 <= 1;
			out1 <= 1;
		end
		3:
		begin
			out0 <= 0;
			out1 <= 1;
		end
		4:
		begin
			out0 <= 2;
			out1 <= 2;
		end
		5:
		begin
			out0 <= 1;
			out1 <= 0;
		end
		6:
		begin
			out0 <= 1;
			out1 <= 2;
		end
		7:
		begin
			out0 <= 3;
			out1 <= 2;
		end
		8:
		begin
			out0 <= 3;
			out1 <= 0;
		end
		9:
		begin
			out0 <= 0;
			out1 <= 2;
		end
		10:
		begin
			out0 <= 2;
			out1 <= 1;
		end
		11:
		begin
			out0 <= 3;
			out1 <= 1;
		end
		12:
		begin
			out0 <= 2;
			out1 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		endcase
		end
	end
endmodule

module multiplication_mod_17(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	output [4:0] out;
	wire [4:0] out_pre;
	wire [4:0] w_1_0;
	wire [4:0] w_2_0;
	wire [4:0] wout_0;
	lut_input_17 lut1(clk, reset, inp1, w_1_0);
	lut_input_17 lut2(clk, reset, inp2, w_2_0);
	sum_modulo_16 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	lut_output_17 lut3(clk, reset, wout_0, out_pre);
	singularity_pass_17 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_17 (in_singular, in2, out);
	input in_singular;
	input [4:0] in2;
	output reg [4:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_17 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	input [4:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [4:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_17 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module sum_modulo_16(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	output reg [4:0] out;
	wire [5:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 16)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 16;
		end
	end
endmodule

module lut_output_17(clk, reset, inp0, out);
	input clk;
	input reset;
	output reg [4:0] out;
	input [4:0] inp0;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 14)
		begin
			out <= 2;
		end
		else if (inp0 == 1)
		begin
			out <= 3;
		end
		else if (inp0 == 12)
		begin
			out <= 4;
		end
		else if (inp0 == 5)
		begin
			out <= 5;
		end
		else if (inp0 == 15)
		begin
			out <= 6;
		end
		else if (inp0 == 11)
		begin
			out <= 7;
		end
		else if (inp0 == 10)
		begin
			out <= 8;
		end
		else if (inp0 == 2)
		begin
			out <= 9;
		end
		else if (inp0 == 3)
		begin
			out <= 10;
		end
		else if (inp0 == 7)
		begin
			out <= 11;
		end
		else if (inp0 == 13)
		begin
			out <= 12;
		end
		else if (inp0 == 4)
		begin
			out <= 13;
		end
		else if (inp0 == 9)
		begin
			out <= 14;
		end
		else if (inp0 == 6)
		begin
			out <= 15;
		end
		else if (inp0 == 8)
		begin
			out <= 16;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_17(clk, reset, inp, out0);
	input clk;
	input reset;
	input [4:0] inp;
	output reg [4:0] out0;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
		end
		2:
		begin
			out0 <= 14;
		end
		3:
		begin
			out0 <= 1;
		end
		4:
		begin
			out0 <= 12;
		end
		5:
		begin
			out0 <= 5;
		end
		6:
		begin
			out0 <= 15;
		end
		7:
		begin
			out0 <= 11;
		end
		8:
		begin
			out0 <= 10;
		end
		9:
		begin
			out0 <= 2;
		end
		10:
		begin
			out0 <= 3;
		end
		11:
		begin
			out0 <= 7;
		end
		12:
		begin
			out0 <= 13;
		end
		13:
		begin
			out0 <= 4;
		end
		14:
		begin
			out0 <= 9;
		end
		15:
		begin
			out0 <= 6;
		end
		16:
		begin
			out0 <= 8;
		end
		default:
		begin
			out0 <= 0;
		end
		endcase
		end
	end
endmodule

module multiplication_mod_19(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	output [4:0] out;
	wire [4:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	wire [3:0] w_1_1;
	wire [3:0] w_2_1;
	wire [3:0] wout_1;
	lut_input_19 lut1(clk, reset, inp1, w_1_0, w_1_1);
	lut_input_19 lut2(clk, reset, inp2, w_2_0, w_2_1);
	sum_modulo_2 sm0(clk, reset, w_1_0, w_2_0, wout_0);
	sum_modulo_9 sm1(clk, reset, w_1_1, w_2_1, wout_1);
	lut_output_19 lut3(clk, reset, wout_0, wout_1, out_pre);
	singularity_pass_19 sp (clk, reset, inp1, inp2, out_pre, out);
endmodule

module singularity_output_choice_19 (in_singular, in2, out);
	input in_singular;
	input [4:0] in2;
	output reg [4:0] out;
			
	always @ (*)
	begin
		if (in_singular == 0)
		begin
			out <= 0;
		end
		else
		begin
			out <= in2;
		end
	end
endmodule

module singularity_pass_19 (clk, reset, inp1, inp2, real_out, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	input [4:0] real_out;
	reg data1;
	wire data2;
	wire data3;
	output [4:0] out;
			
	singular s1 (clk, reset, data1, data2);
	singular s2 (clk, reset, data2, data3);
	singularity_output_choice_19 soc (data3, real_out, out);
			
	always @ (posedge clk)
	begin
		if (inp1 == 0 || inp2 == 0 || reset == 1'b1)
			data1 <= 0;
		else
			data1 <= 1;
	end
endmodule

module sum_modulo_9(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	output reg [3:0] out;
	wire [4:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 9)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 9;
		end
	end
endmodule

module lut_output_19(clk, reset, inp0, inp1, out);
	input clk;
	input reset;
	output reg [4:0] out;
	input [1:0] inp0;
	input [3:0] inp1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out <= 0;
		end
		else if (inp0 == 0 && inp1 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 1 && inp1 == 1)
		begin
			out <= 2;
		end
		else if (inp0 == 1 && inp1 == 4)
		begin
			out <= 3;
		end
		else if (inp0 == 0 && inp1 == 2)
		begin
			out <= 4;
		end
		else if (inp0 == 0 && inp1 == 7)
		begin
			out <= 5;
		end
		else if (inp0 == 0 && inp1 == 5)
		begin
			out <= 6;
		end
		else if (inp0 == 0 && inp1 == 6)
		begin
			out <= 7;
		end
		else if (inp0 == 1 && inp1 == 3)
		begin
			out <= 8;
		end
		else if (inp0 == 0 && inp1 == 8)
		begin
			out <= 9;
		end
		else if (inp0 == 1 && inp1 == 8)
		begin
			out <= 10;
		end
		else if (inp0 == 0 && inp1 == 3)
		begin
			out <= 11;
		end
		else if (inp0 == 1 && inp1 == 6)
		begin
			out <= 12;
		end
		else if (inp0 == 1 && inp1 == 5)
		begin
			out <= 13;
		end
		else if (inp0 == 1 && inp1 == 7)
		begin
			out <= 14;
		end
		else if (inp0 == 1 && inp1 == 2)
		begin
			out <= 15;
		end
		else if (inp0 == 0 && inp1 == 4)
		begin
			out <= 16;
		end
		else if (inp0 == 0 && inp1 == 1)
		begin
			out <= 17;
		end
		else if (inp0 == 1 && inp1 == 0)
		begin
			out <= 18;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_19(clk, reset, inp, out0, out1);
	input clk;
	input reset;
	input [4:0] inp;
	output reg [1:0] out0;
	output reg [3:0] out1;
	always @ (posedge clk)
	begin
		if (reset == 1'b1) begin
			out0 <= 0;
			out1 <= 0;
		end
		else
		begin
		case(inp)
		1:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		2:
		begin
			out0 <= 1;
			out1 <= 1;
		end
		3:
		begin
			out0 <= 1;
			out1 <= 4;
		end
		4:
		begin
			out0 <= 0;
			out1 <= 2;
		end
		5:
		begin
			out0 <= 0;
			out1 <= 7;
		end
		6:
		begin
			out0 <= 0;
			out1 <= 5;
		end
		7:
		begin
			out0 <= 0;
			out1 <= 6;
		end
		8:
		begin
			out0 <= 1;
			out1 <= 3;
		end
		9:
		begin
			out0 <= 0;
			out1 <= 8;
		end
		10:
		begin
			out0 <= 1;
			out1 <= 8;
		end
		11:
		begin
			out0 <= 0;
			out1 <= 3;
		end
		12:
		begin
			out0 <= 1;
			out1 <= 6;
		end
		13:
		begin
			out0 <= 1;
			out1 <= 5;
		end
		14:
		begin
			out0 <= 1;
			out1 <= 7;
		end
		15:
		begin
			out0 <= 1;
			out1 <= 2;
		end
		16:
		begin
			out0 <= 0;
			out1 <= 4;
		end
		17:
		begin
			out0 <= 0;
			out1 <= 1;
		end
		18:
		begin
			out0 <= 1;
			out1 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		endcase
		end
	end
endmodule

module sum_modulo_7(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [2:0] inp1;
	input [2:0] inp2;
	output reg [2:0] out;
	wire [3:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 7)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 7;
		end
	end
endmodule

module sum_modulo_11(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	output reg [3:0] out;
	wire [4:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 11)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 11;
		end
	end
endmodule

module sum_modulo_13(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [3:0] inp1;
	input [3:0] inp2;
	output reg [3:0] out;
	wire [4:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 13)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 13;
		end
	end
endmodule

module sum_modulo_17(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	output reg [4:0] out;
	wire [5:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 17)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 17;
		end
	end
endmodule

module sum_modulo_19(clk, reset, inp1, inp2, out);
	input clk;
	input reset;
	input [4:0] inp1;
	input [4:0] inp2;
	output reg [4:0] out;
	wire [5:0] int;
	assign int = inp1 + inp2;
	always @ (posedge clk)
	begin
		if (reset == 1'b1)
		begin
			out <= 0;
		end
		else if (int < 19)
		begin
			out <= int;
		end
		else
		begin
			out <= int - 19;
		end
	end
endmodule

module a_test_bench();
	reg clock;
	reg reset;
	reg [7:0] a, b;
	wire [1:0] out_3;
	wire [2:0] out_5;
	wire [2:0] out_7;
	wire [3:0] out_11;
	wire [3:0] out_13;
	wire [4:0] out_17;
	wire [4:0] out_19;
	integer expected = 0;
	integer dummy = 0;
	integer prev[4:0];

	scalar_multiply s1 (clock, reset, a, b, out_3, out_5, out_7, out_11, out_13, out_17, out_19);
	
	// Initialize all variables
	initial begin        
	$display ("Start!");
	clock = 1;  // initial value of clock
	reset = 0;  // initial value of reset
	a = 0;      // initial value of a
	b = 0;      // initial value of b
	prev[0] = 0;
	prev[1] = 0;
	prev[2] = 0;
	prev[3] = 0;
	prev[4] = 0;
	#1 clock = 0;
	#1 reset = 1;
	#1 clock = 1;
	#1 reset = 0;
	#1 clock = 0;
	#1 clock = 0;
	#1 a = 176;
	#1 b = 147;
	#1 clock = 1;
	#1 dummy = 1;
	// Result without delay: 25872 ( 0 2 0 0 2 15 13)
	$display ("( %d %d %d %d %d %d %d) Expect: ( %d %d %d %d %d %d %d)", out_3, out_5, out_7, out_11, out_13, out_17, out_19, prev[4]%3, prev[4]%5, prev[4]%7, prev[4]%11, prev[4]%13, prev[4]%17, prev[4]%19);
	prev[4] = prev[3];
	prev[3] = prev[2];
	prev[2] = prev[1];
	prev[1] = prev[0];
	prev[0] = 15'd25872;

	#1 clock = 0;
	#1 a = 53;
	#1 b = 60;
	#1 clock = 1;
	#1 dummy = 1;
	// Result without delay: 29052 ( 0 2 2 1 10 16 1)
	$display ("( %d %d %d %d %d %d %d) Expect: ( %d %d %d %d %d %d %d)", out_3, out_5, out_7, out_11, out_13, out_17, out_19, prev[4]%3, prev[4]%5, prev[4]%7, prev[4]%11, prev[4]%13, prev[4]%17, prev[4]%19);
	prev[4] = prev[3];
	prev[3] = prev[2];
	prev[2] = prev[1];
	prev[1] = prev[0];
	prev[0] = 15'd29052;

	#1 clock = 0;
	#1 a = 43;
	#1 b = 153;
	#1 clock = 1;
	#1 dummy = 1;
	// Result without delay: 35631 ( 0 1 1 2 11 16 6)
	$display ("( %d %d %d %d %d %d %d) Expect: ( %d %d %d %d %d %d %d)", out_3, out_5, out_7, out_11, out_13, out_17, out_19, prev[4]%3, prev[4]%5, prev[4]%7, prev[4]%11, prev[4]%13, prev[4]%17, prev[4]%19);
	prev[4] = prev[3];
	prev[3] = prev[2];
	prev[2] = prev[1];
	prev[1] = prev[0];
	prev[0] = 16'd35631;

	#1 clock = 0;
	#1 a = 95;
	#1 b = 166;
	#1 clock = 1;
	#1 dummy = 1;
	// Result without delay: 51401 ( 2 1 0 9 12 10 6)
	$display ("( %d %d %d %d %d %d %d) Expect: ( %d %d %d %d %d %d %d)", out_3, out_5, out_7, out_11, out_13, out_17, out_19, prev[4]%3, prev[4]%5, prev[4]%7, prev[4]%11, prev[4]%13, prev[4]%17, prev[4]%19);
	prev[4] = prev[3];
	prev[3] = prev[2];
	prev[2] = prev[1];
	prev[1] = prev[0];
	prev[0] = 16'd51401;

	#1 clock = 0;
	$display ("Stop!");
	#1 clock = 1;
	end
endmodule
Описание:
1) Задержка между данными и получением ответа на выходе устройства ровно 6 тактов: 2 такта конвейера прямое преобразование, 3 такта конвейера умножение и последний такт конвейера на сложение.
2) Отсутствует обратное преобразование результата, которое будет выполняться всего один раз в самом конце вычислений. Для этого можно использовать модуль отсюда: конвейерный обратный преобразователь на базе полиадического кода или отсюда конвейерный обратный преобразователь на базе полиадического кода с коррекцией ошибок".
3) Test bench может работать некорректно на данных выходящих за 32 бита. Но сама схема должна работать корректно.