Генератор Verilog конвеерного обратного преобразователя на базе полиадического кода с коррекцией ошибок

* - Модули должны быть взаимнопросты
* - Два старших модуля используются для коррекции
* - Если данные выйдут за 32 бита, корректность пока не гарантируется
Информационные модули: 3 5
Проверочные модули: 7 11
Динамический диапазон: 15
module lut_3_5(out, a, b, clk);
	input [1:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 2*inter[0] + 4*inter[1] + 3*inter[2];
	mod_5_9 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 5 + b - a;
		end 
	end
endmodule

module mod_5_9 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd5)
		begin
			out = in;
		end
		else
		begin
			out = in - 3'd5;
		end
	end
endmodule

module lut_3_7(out, a, b, clk);
	input [1:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 5*inter[0] + 3*inter[1] + 6*inter[2];
	mod_7_14 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 7 + b - a;
		end 
	end
endmodule

module mod_7_14 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd7)
		begin
			out = in;
		end
		else if (in < 4'd14)
		begin
			out = in - 3'd7;
		end
		else
		begin
			out = in - 4'd14;
		end
	end
endmodule

module lut_3_11(out, a, b, clk);
	input [1:0] a;
	input [3:0] b;
	reg [3:0] inter;
	wire [4:0] bmod;
	input clk;
	output wire [3:0] out;

	assign bmod = 4*inter[0] + 8*inter[1] + 5*inter[2] + 10*inter[3];
	mod_11_27 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 11 + b - a;
		end 
	end
endmodule

module mod_11_27 (in, out);
	input [4:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
		if (in < 4'd11)
		begin
			out = in;
		end
		else if (in < 5'd22)
		begin
			out = in - 4'd11;
		end
		else
		begin
			out = in - 5'd22;
		end
	end
endmodule

module lut_5_7(out, a, b, clk);
	input [2:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 3*inter[0] + 6*inter[1] + 5*inter[2];
	mod_7_14 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 7 + b - a;
		end 
	end
endmodule

module lut_5_11(out, a, b, clk);
	input [2:0] a;
	input [3:0] b;
	reg [3:0] inter;
	wire [4:0] bmod;
	input clk;
	output wire [3:0] out;

	assign bmod = 9*inter[0] + 7*inter[1] + 3*inter[2] + 6*inter[3];
	mod_11_25 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 11 + b - a;
		end 
	end
endmodule

module mod_11_25 (in, out);
	input [4:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
		if (in < 4'd11)
		begin
			out = in;
		end
		else if (in < 5'd22)
		begin
			out = in - 4'd11;
		end
		else
		begin
			out = in - 5'd22;
		end
	end
endmodule

module lut_7_11(out, a, b, clk);
	input [2:0] a;
	input [3:0] b;
	reg [3:0] inter;
	wire [5:0] bmod;
	input clk;
	output wire [3:0] out;

	assign bmod = 8*inter[0] + 5*inter[1] + 10*inter[2] + 9*inter[3];
	mod_11_32 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 11 + b - a;
		end 
	end
endmodule

module mod_11_32 (in, out);
	input [5:0] in;
	output reg [3:0] out;
	always @ (in)
	begin
		if (in < 4'd11)
		begin
			out = in;
		end
		else if (in < 5'd22)
		begin
			out = in - 4'd11;
		end
		else
		begin
			out = in - 5'd22;
		end
	end
endmodule

module register(res, x, clk);
	parameter WIDTH=3;
	input  clk;
	input  [WIDTH-1:0] x;
	output reg [WIDTH-1:0] res;

	always @ (posedge clk)
	begin
		res <= x;
	end
endmodule

module error_correction_step (out, inp_p1_1, inp_p1_2, inp_p1_3, inp_p2_1, inp_p2_2, inp_p2_3, inp_p3_1, inp_p3_2, inp_p3_3, inp_p4_1, inp_p4_2, inp_p4_3, clk); 

	input clk;
	output reg [3:0] out;

	input [2:0] inp_p1_1;
	input [2:0] inp_p1_2;
	input [3:0] inp_p1_3;
	input [1:0] inp_p2_1;
	input [2:0] inp_p2_2;
	input [3:0] inp_p2_3;
	input [1:0] inp_p3_1;
	input [2:0] inp_p3_2;
	input [3:0] inp_p3_3;
	input [1:0] inp_p4_1;
	input [2:0] inp_p4_2;
	input [2:0] inp_p4_3;
	
	always @ (posedge clk) 
	begin 
		if (inp_p1_3 == 0)
		begin 
			out = inp_p1_1 + inp_p1_2*5;
		end
		else if (inp_p2_3 == 0)
		begin 
			out = inp_p2_1 + inp_p2_2*3;
		end
		else if (inp_p3_3 == 0)
		begin 
			out = inp_p3_1 + inp_p3_2*3;
		end
		else if (inp_p4_3 == 0)
		begin 
			out = inp_p4_1 + inp_p4_2*3;
		end
	end
endmodule

module reverse_conv_with_error_correction (out, x1, x2, x3, x4, clk); 

	input clk;
	input [1:0] x1;
	input [2:0] x2;
	input [2:0] x3;
	input [3:0] x4;
	output [3:0] out;

	wire [2:0] out_p1_1;
	wire [2:0] out_p1_2;
	wire [3:0] out_p1_3;
	wire [1:0] out_p2_1;
	wire [2:0] out_p2_2;
	wire [3:0] out_p2_3;
	wire [1:0] out_p3_1;
	wire [2:0] out_p3_2;
	wire [3:0] out_p3_3;
	wire [1:0] out_p4_1;
	wire [2:0] out_p4_2;
	wire [2:0] out_p4_3;
	

	// Print S1
	wire [1:0] inter_s1_1_1;
	register #(.WIDTH(2)) reg_s1_1_1 (inter_s1_1_1, x1, clk);
	wire [2:0] inter_s1_1_2;
	lut_3_5 lut_s1_1_2 (inter_s1_1_2, x1, x2, clk);
	wire [2:0] inter_s1_1_3;
	lut_3_7 lut_s1_1_3 (inter_s1_1_3, x1, x3, clk);
	wire [3:0] inter_s1_1_4;
	lut_3_11 lut_s1_1_4 (inter_s1_1_4, x1, x4, clk);
	wire [1:0] out_s1_1;
	register #(.WIDTH(2)) reg_s1_2_1 (out_s1_1, inter_s1_1_1, clk);
	wire [2:0] out_s1_2;
	register #(.WIDTH(3)) reg_s1_2_2 (out_s1_2, inter_s1_1_2, clk);
	wire [2:0] out_s1_3;
	lut_5_7 lut_s1_2_3 (out_s1_3, inter_s1_1_2, inter_s1_1_3, clk);
	wire [3:0] out_s1_4;
	lut_5_11 lut_s1_2_4 (out_s1_4, inter_s1_1_2, inter_s1_1_4, clk);

	// Print S2
	wire [2:0] inter_s2_1_2;
	register #(.WIDTH(3)) reg_s2_1_1 (inter_s2_1_2, x2, clk);
	wire [2:0] inter_s2_1_3;
	lut_5_7 lut_s2_1_2 (inter_s2_1_3, x2, x3, clk);
	wire [3:0] inter_s2_1_4;
	lut_5_11 lut_s2_1_3 (inter_s2_1_4, x2, x4, clk);
	wire [2:0] out_s2_2;
	register #(.WIDTH(3)) reg_s2_2_1 (out_s2_2, inter_s2_1_2, clk);
	wire [2:0] out_s2_3;
	register #(.WIDTH(3)) reg_s2_2_2 (out_s2_3, inter_s2_1_3, clk);
	wire [3:0] out_s2_4;
	lut_7_11 lut_s2_2_3 (out_s2_4, inter_s2_1_3, inter_s2_1_4, clk);

	// Print S3
	wire [2:0] out_s3_3;
	register #(.WIDTH(3)) reg_s3_1_1 (out_s3_3, inter_s1_1_3, clk);
	wire [3:0] out_s3_4;
	lut_7_11 lut_s3_1_2 (out_s3_4, inter_s1_1_3, inter_s1_1_4, clk);

	// Partial backward excluding x4
	assign out_p4_1 = out_s1_1;
	assign out_p4_2 = out_s1_2;
	assign out_p4_3 = out_s1_3;

	// Partial backward excluding x3
	assign out_p3_1 = out_s1_1;
	assign out_p3_2 = out_s1_2;
	assign out_p3_3 = out_s1_4;

	// Partial backward excluding x2
	assign out_p2_1 = out_s1_1;
	assign out_p2_2 = out_s3_3;
	assign out_p2_3 = out_s3_4;

	// Partial backward excluding x1
	assign out_p1_1 = out_s2_2;
	assign out_p1_2 = out_s2_3;
	assign out_p1_3 = out_s2_4;

	error_correction_step ecorr (out, out_p1_1, out_p1_2, out_p1_3, out_p2_1, out_p2_2, out_p2_3, out_p3_1, out_p3_2, out_p3_3, out_p4_1, out_p4_2, out_p4_3, clk);
endmodule

module atest_bench();
	reg clk;
	reg [1:0] in0;  // Module: 3
	reg [1:0] inreal0;
	reg [2:0] in1;  // Module: 5
	reg [2:0] inreal1;
	reg [2:0] in2;  // Module: 7
	reg [2:0] inreal2;
	reg [3:0] in3;  // Module: 11
	reg [3:0] inreal3;
	wire [3:0] out; // Max value (not included): 15

	integer l, modnum, errdigit;
	reg dummy;
	integer i0;
	integer prev[4:0];
	integer mod[4:0];

	reverse_conv_with_error_correction r1 (out, in0, in1, in2, in3, clk);

	// One test. Ticks: 3
	initial
	begin
	mod[0] = 3;
	mod[1] = 5;
	mod[2] = 7;
	mod[3] = 11;
	prev[0] = -1;
	prev[1] = -1;
	prev[2] = -1;
	prev[3] = -1;
	for (i0 = 0; i0 < 15; i0 = i0+1)
	begin
	for (modnum = 0; modnum < 4; modnum = modnum+1)
	begin
	for (errdigit = 0; errdigit < mod[modnum]; errdigit = errdigit+1)
	begin
		#1 dummy = 1;
		clk = 0;
		#1 dummy = 1;
		if (modnum == 0)
		begin
			in0 = errdigit;
		end
		else
		begin
			in0 = i0%mod[0];
		end
		inreal0 = i0%mod[0];
		if (modnum == 1)
		begin
			in1 = errdigit;
		end
		else
		begin
			in1 = i0%mod[1];
		end
		inreal1 = i0%mod[1];
		if (modnum == 2)
		begin
			in2 = errdigit;
		end
		else
		begin
			in2 = i0%mod[2];
		end
		inreal2 = i0%mod[2];
		if (modnum == 3)
		begin
			in3 = errdigit;
		end
		else
		begin
			in3 = i0%mod[3];
		end
		inreal3 = i0%mod[3];
		#1 dummy = 1;
		clk = 1;
		#1 dummy = 1;
		// Value for check (based on length of pipeline)
		if (prev[2] >= 0)
		begin
			$display ("!!! IN SHOULD BE: (%d %d %d %d ) IN ERRORUS: (%d %d %d %d )  Res=(%d) Expect=(%d)", inreal0, inreal1, inreal2, inreal3, in0, in1, in2, in3, out, prev[2]);
			l = out;
			if (l != prev[2])
			begin
				$display ("!!! Error (%d, %d)!!!", prev[2], l);
			end
		end
		prev[0] = prev[1];
		prev[1] = prev[2];
		prev[2] = prev[3];
		prev[3] = i0;
	end
	end
	end
	end
endmodule
Описание:
1. Испольуется подход на базе полиадического кода
2. Количество тактов для расчета равно количеству модулей