Генератор Verilog конвеерного обратного преобразователя на базе полиадического кода

* - Модули должны быть взаимнопросты

* - Если данные выйдут за 32 бита, корректность пока не гарантируется

Набор модулей: 3 5 7
Набор коэффициентов: 1 3 15

module lut_3_5(out, a, b, clk);
	input [1:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 2*inter[0] + 4*inter[1] + 3*inter[2];
	mod_5_9 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 5 + b - a;
		end 
	end
endmodule

module mod_5_9 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd5)
		begin
			out = in;
		end
		else
		begin
			out = in - 3'd5;
		end
	end
endmodule

module lut_3_7(out, a, b, clk);
	input [1:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 5*inter[0] + 3*inter[1] + 6*inter[2];
	mod_7_14 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 7 + b - a;
		end 
	end
endmodule

module mod_7_14 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd7)
		begin
			out = in;
		end
		else if (in < 4'd14)
		begin
			out = in - 3'd7;
		end
		else
		begin
			out = in - 4'd14;
		end
	end
endmodule

module lut_5_7(out, a, b, clk);
	input [2:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 3*inter[0] + 6*inter[1] + 5*inter[2];
	mod_7_14 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 7 + b - a;
		end 
	end
endmodule

module mult5(out, data);

	input [2:0] data;
	output reg [3:0] out;
	
	always @ (data) 
	begin
		out <= 3*data;
	end
endmodule

module mult7(out, data);

	input [2:0] data;
	output reg [6:0] out;
	
	always @ (data) 
	begin
		out <= 15*data;
	end
endmodule

module register(res, x, clk);
	parameter WIDTH=3;
	input  clk;
	input  [WIDTH-1:0] x;
	output reg [WIDTH-1:0] res;

	always @ (posedge clk)
	begin
		res <= x;
	end
endmodule

module adder(result, dataa, datab, clk);
	parameter WIDTH_A=3;
	parameter WIDTH_B=8;
	parameter WIDTH_C=8;
	input clk;
	input  [WIDTH_A - 1:0] dataa;
	input  [WIDTH_B - 1:0] datab;
	output reg [WIDTH_C:0] result;

	always @ (posedge clk) 
	begin 
		result <= dataa + datab;
	end
endmodule

module mix_rdx (res1, res2, res3, x1, x2, x3, clk); 

	input clk;
	input	[1:0] x1;
	input	[2:0] x2;
	input	[2:0] x3;

	output	[1:0] res1;
	output	[2:0] res2;
	output	[2:0] res3;
	
	wire [2:0] out_3_7;

	assign res1 = x1;

	lut_3_5 l3_5 (res2, x1, x2, clk);
	lut_3_7 l3_7 (out_3_7, x1, x3, clk);
	lut_5_7 l5_7 (res3, res2, out_3_7, clk);
endmodule

module par_adder(result, x1, x2, x3, clk);

	input clk;
	input [1:0] x1;
	input [3:0] x2;
	input [6:0] x3;
	output [6:0] result;
	wire [1:0] reg1out;
	wire [4:0] add1out;

	register #(.WIDTH(2)) reg1 (reg1out, x1, clk);
	adder #(.WIDTH_A(2), .WIDTH_B(4), .WIDTH_C(4)) add1 (add1out, reg1out, x2, clk);
	adder #(.WIDTH_A(5), .WIDTH_B(7), .WIDTH_C(6)) add2 (result, add1out, x3, clk);
endmodule

module reverse_conv(result, x1, x2, x3, clk);

	input clk;
	input [1:0] x1;
	input [2:0] x2;
	input [2:0] x3;
	output [6:0] result;

	wire [1:0] mix_rdx1out;
	wire [2:0] mix_rdx2out;
	wire [2:0] mix_rdx3out;

	wire [3:0] mult5out;
	wire [6:0] mult7out;
	mix_rdx mix1 (mix_rdx1out, mix_rdx2out, mix_rdx3out, x1, x2, x3, clk);
	mult5 m5 (mult5out, mix_rdx2out);
	mult7 m7 (mult7out, mix_rdx3out);
	par_adder pa (result, mix_rdx1out, mult5out, mult7out, clk);

endmodule

module atest_bench();
	reg clk;
	reg [1:0] in0;  // Module: 3
	reg [2:0] in1;  // Module: 5
	reg [2:0] in2;  // Module: 7
	wire [6:0] out; // Max value (not included): 105

	integer l;
	reg dummy;
	integer i0, prev;

	reverse_conv r1 (out, in0, in1, in2, clk);

	// One test. Ticks: 3
	initial
	begin
	// Main cycle
	for (i0 = 0; i0 < 105; i0 = i0+1)
	begin
		#1 dummy = 1;
		clk = 0;
		#1 dummy = 1;
		in0 = i0%3;
		in1 = i0%5;
		in2 = i0%7;
		#1 dummy = 1;
		clk = 1;
		#1 dummy = 1;
		// Value for check (based on length of pipeline)
		prev = i0-3+1; 
		if (prev >= 0)
		begin
			$display ("!!! Res=(%d) Expect=(%d)", out, prev);
			l = out;
			if (l != prev)
			begin
				$display ("!!! Error (%d, %d)!!!", prev, l);
			end
		end
	end
	// Last data on pipeline
	for (i0 = 105; i0 < 105 + 3 - 1; i0 = i0+1)
	begin
		#1 dummy = 1;
		clk = 0;
		#1 dummy = 1;
		clk = 1;
		#1 dummy = 1;
		// Value for check
		prev = i0-3+1; 
		$display ("!!! Res=(%d) Expect=(%d)", out, prev);
		l = out;
		if (l != prev)
		begin
			$display ("!!! Error (%d, %d)!!!", prev, l);
		end
	end
	end
endmodule

Описание:
1. Испольуется подход на базе полиадического кода
2. Количество тактов для расчета равно количеству модулей