Генератор Verilog конвеерного обратного преобразователя на базе полиадического кода с коррекцией ошибок

* - Модули должны быть взаимнопросты

* - Если данные выйдут за 32 бита, корректность пока не гарантируется

* - Используется стандартный метод проекций

Набор модулей: 3 5 7
Базовые модули: 3
Проверочные модули: 5 7

module lut_3_5(out, a, b, clk);
	input [1:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 2*inter[0] + 4*inter[1] + 3*inter[2];
	mod_5_9 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 5 + b - a;
		end 
	end
endmodule

module mod_5_9 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd5)
		begin
			out = in;
		end
		else
		begin
			out = in - 3'd5;
		end
	end
endmodule

module lut_3_7(out, a, b, clk);
	input [1:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 5*inter[0] + 3*inter[1] + 6*inter[2];
	mod_7_14 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 7 + b - a;
		end 
	end
endmodule

module mod_7_14 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
		if (in < 3'd7)
		begin
			out = in;
		end
		else if (in < 4'd14)
		begin
			out = in - 3'd7;
		end
		else
		begin
			out = in - 4'd14;
		end
	end
endmodule

module lut_5_7(out, a, b, clk);
	input [2:0] a;
	input [2:0] b;
	reg [2:0] inter;
	wire [3:0] bmod;
	input clk;
	output wire [2:0] out;

	assign bmod = 3*inter[0] + 6*inter[1] + 5*inter[2];
	mod_7_14 mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 7 + b - a;
		end 
	end
endmodule

module mult_1_7(out, data);

	input [2:0] data;
	output reg [4:0] out;
	
	always @ (data) 
	begin
		out <= 5*data;
	end
endmodule

module mix_rdx_1 (res1, res2, x1, x2, clk); 

	input clk;
	input	[2:0] x1;
	input	[2:0] x2;

	output	[2:0] res1;
	output	[2:0] res2;
	

	assign res1 = x1;

	lut_5_7 l5_7 (res2, x1, x2, clk);
endmodule

module par_adder_1(result, x1, x2, clk);

	input clk;
	input [2:0] x1;
	input [4:0] x2;
	output [4:0] result;
	wire [2:0] reg1out;

	register #(.WIDTH(3)) reg1 (reg1out, x1, clk);
	adder #(.WIDTH_A(3), .WIDTH_B(5), .WIDTH_C(5)) add1 (add1out, reg1out, x2, clk);
	adder #(.WIDTH_A(4), .WIDTH_B(5), .WIDTH_C(4)) add1 (result, add0out, x2, clk);
endmodule

module reverse_conv_1(result, flag, x1, x2, clk);

	input clk;
	input [2:0] x1;
	input [2:0] x2;
	output [4:0] result;
	output flag;

	wire [2:0] mix_rdx1out;
	wire [2:0] mix_rdx2out;

	wire [4:0] mult7out;
	assign flag = mix_rdx2out[0] | mix_rdx2out[1] | mix_rdx2out[2];
	mix_rdx_1 mix1 (mix_rdx1out, mix_rdx2out, x1, x2, clk);
	mult_1_7 m7 (mult7out, mix_rdx2out);
	par_adder_1 pa (result, mix_rdx1out, mult7out, clk);

endmodule

module mult_2_7(out, data);

	input [2:0] data;
	output reg [4:0] out;
	
	always @ (data) 
	begin
		out <= 3*data;
	end
endmodule

module mix_rdx_2 (res1, res2, x1, x2, clk); 

	input clk;
	input	[1:0] x1;
	input	[2:0] x2;

	output	[1:0] res1;
	output	[2:0] res2;
	

	assign res1 = x1;

	lut_3_7 l3_7 (res2, x1, x2, clk);
endmodule

module par_adder_2(result, x1, x2, clk);

	input clk;
	input [1:0] x1;
	input [4:0] x2;
	output [4:0] result;
	wire [1:0] reg1out;

	register #(.WIDTH(2)) reg1 (reg1out, x1, clk);
	adder #(.WIDTH_A(2), .WIDTH_B(5), .WIDTH_C(5)) add1 (add1out, reg1out, x2, clk);
	adder #(.WIDTH_A(3), .WIDTH_B(5), .WIDTH_C(4)) add1 (result, add0out, x2, clk);
endmodule

module reverse_conv_2(result, flag, x1, x2, clk);

	input clk;
	input [1:0] x1;
	input [2:0] x2;
	output [4:0] result;
	output flag;

	wire [1:0] mix_rdx1out;
	wire [2:0] mix_rdx2out;

	wire [4:0] mult7out;
	assign flag = mix_rdx2out[0] | mix_rdx2out[1] | mix_rdx2out[2];
	mix_rdx_2 mix1 (mix_rdx1out, mix_rdx2out, x1, x2, clk);
	mult_2_7 m7 (mult7out, mix_rdx2out);
	par_adder_2 pa (result, mix_rdx1out, mult7out, clk);

endmodule

module mult_3_5(out, data);

	input [2:0] data;
	output reg [3:0] out;
	
	always @ (data) 
	begin
		out <= 3*data;
	end
endmodule

module mix_rdx_3 (res1, res2, x1, x2, clk); 

	input clk;
	input	[1:0] x1;
	input	[2:0] x2;

	output	[1:0] res1;
	output	[2:0] res2;
	

	assign res1 = x1;

	lut_3_5 l3_5 (res2, x1, x2, clk);
endmodule

module par_adder_3(result, x1, x2, clk);

	input clk;
	input [1:0] x1;
	input [3:0] x2;
	output [3:0] result;
	wire [1:0] reg1out;

	register #(.WIDTH(2)) reg1 (reg1out, x1, clk);
	adder #(.WIDTH_A(2), .WIDTH_B(4), .WIDTH_C(4)) add1 (add1out, reg1out, x2, clk);
	adder #(.WIDTH_A(3), .WIDTH_B(4), .WIDTH_C(3)) add1 (result, add0out, x2, clk);
endmodule

module reverse_conv_3(result, flag, x1, x2, clk);

	input clk;
	input [1:0] x1;
	input [2:0] x2;
	output [3:0] result;
	output flag;

	wire [1:0] mix_rdx1out;
	wire [2:0] mix_rdx2out;

	wire [3:0] mult5out;
	assign flag = mix_rdx2out[0] | mix_rdx2out[1] | mix_rdx2out[2];
	mix_rdx_3 mix1 (mix_rdx1out, mix_rdx2out, x1, x2, clk);
	mult_3_5 m5 (mult5out, mix_rdx2out);
	par_adder_3 pa (result, mix_rdx1out, mult5out, clk);

endmodule

module register(res, x, clk);
	parameter WIDTH=3;
	input  clk;
	input  [WIDTH-1:0] x;
	output reg [WIDTH-1:0] res;

	always @ (posedge clk)
	begin
		res <= x;
	end
endmodule

module adder(result, dataa, datab, clk);
	parameter WIDTH_A=3;
	parameter WIDTH_B=8;
	parameter WIDTH_C=8;
	input clk;
	input  [WIDTH_A - 1:0] dataa;
	input  [WIDTH_B - 1:0] datab;
	output reg [WIDTH_C:0] result;

	always @ (posedge clk) 
	begin 
		result <= dataa + datab;
	end
endmodule

module error_correction (out, x1, x2, x3, clk); 

	input clk;
	output reg [1:0] out;

	input [1:0] x1;
	input [2:0] x2;
	input [2:0] x3;
	wire flag1, flag2, flag3, rflag1, rflag2, rflag3;
	wire [4:0] out1;
	wire [4:0] out2;
	wire [3:0] out3;
	reverse_conv_1 rev1 (out1, flag1, x2, x3, clk);
	reverse_conv_2 rev2 (out2, flag2, x1, x3, clk);
	reverse_conv_3 rev3 (out3, flag3, x1, x2, clk);
	register #(.WIDTH(1)) rg1 (rflag1, flag1, clk);
	register #(.WIDTH(1)) rg2 (rflag2, flag2, clk);
	register #(.WIDTH(1)) rg3 (rflag3, flag3, clk);
	always @ (posedge clk) 
	begin 
	if (rflag1 == 0) 
		begin  
			out = out1[1:0]; 
		end 
	else if (rflag2 == 0) 
		begin  
			out = out2[1:0]; 
		end		 
	else if (rflag3 == 0) 
		begin  
			out = out3[1:0]; 
		end		 
	end
endmodule

Описание:
1. Испольуется подход на базе полиадического кода
2. Количество тактов для расчета равно количеству модулей