Verilog generator for RNS multiplier (positional multiplication with forward conversion)

module mult_mod_7 (in1, in2, out);
	input [2:0] in1; // Max value: 7
	input [2:0] in2; // Max value: 7
	output [2:0] out; // Max value: 7
	wire [5:0] mul; // Max value: 49

	assign mul = in1*in2;
	forward_conv_module_7 fconv(mul, out);
endmodule

module forward_conv_module_7 (in, out);
	input [5:0] in; // Max value: 63
	output [2:0] out; // Max value: 6
	wire [3:0] inter1; // Max value: 14
	assign inter1 = in[2:0] + in[3] + 2*in[4] + 4*in[5];
	mod_7_14 inst(inter1, out);
endmodule

module mod_7_14 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 0;
		8: out = 1;
		9: out = 2;
		10: out = 3;
		11: out = 4;
		12: out = 5;
		13: out = 6;
		14: out = 0;
		default: out = 0;
	endcase
	end
endmodule

module a_test_bench();
	reg [2:0] in1;
	reg [2:0] in2;
	wire [2:0] out; // Module: 7
	integer l;
	reg dummy;
	integer fori, forj;
	integer modres;
	mult_mod_7 mm (in1, in2, out);
	initial
	begin
		for (fori = 0; fori < 3'd7; fori = fori + 1)
		begin
		for (forj = 0; forj < 3'd7; forj = forj + 1)
		begin
			in1 = fori;
			in2 = forj;
			#1 dummy = 1;
			$display ("! In1 = %d, In2 = %d, Res=(%d), Expect=(%d)", fori, forj, out, (fori*forj)%7);
			modres = out;
			if (modres != (fori*forj)%7)
			begin
				$display ("!!! Error (%d, %d)!!!", (fori*forj)%7, modres);
			end
			#1 dummy = 1;
		end
		end
	end
endmodule

Описание:

1) Модулярный умножитель сделанный на базе позиционного с последующим прямым преобразователем. Из-за небольшой входной битности, оба блока получаются довольно компактными.