Генератор Verilog для умножителя по модулю на базе частичных сумм

Введите модуль:

module mult_mod_7 (in1, in2, out);
	input [2:0] in1;
	input [2:0] in2;
	output [2:0] out;
	wire [3:0] inter;
	// Maxval: 11 (Achieved on pair 3, 6)
	assign inter = in1[0]*in2[0] + 2*in1[0]*in2[1] + 4*in1[0]*in2[2] + 2*in1[1]*in2[0] + 4*in1[1]*in2[1] + in1[1]*in2[2] + 4*in1[2]*in2[0] + in1[2]*in2[1] + 2*in1[2]*in2[2];
	mod_7_11 m(inter, out);
endmodule

module mod_7_11 (in, out);
	input [3:0] in;
	output reg [2:0] out;
	always @ (in)
	begin
	// we have small max value so we can use table here
	case (in)
		0: out = 0;
		1: out = 1;
		2: out = 2;
		3: out = 3;
		4: out = 4;
		5: out = 5;
		6: out = 6;
		7: out = 0;
		8: out = 1;
		9: out = 2;
		10: out = 3;
		11: out = 4;
		default: out = 0;
	endcase
	end
endmodule

module a_test_bench();
	reg [2:0] in1;
	reg [2:0] in2;
	wire [2:0] out; // Module: 7
	integer l;
	reg dummy;
	integer fori, forj;
	integer modres;
	mult_mod_7 mm (in1, in2, out);
	initial
	begin
		for (fori = 0; fori < 3'd7; fori = fori + 1)
		begin
		for (forj = 0; forj < 3'd7; forj = forj + 1)
		begin
			in1 = fori;
			in2 = forj;
			#1 dummy = 1;
			$display ("! In1 = %d, In2 = %d, Res=(%d), Expect=(%d)", fori, forj, out, (fori*forj)%7);
			modres = out;
			if (modres != (fori*forj)%7)
			begin
				$display ("!!! Error (%d, %d)!!!", (fori*forj)%7, modres);
			end
			#1 dummy = 1;
		end
		end
	end
endmodule

Описание:

1) Модулярный умножитель сделанный на базе частичных сумм с редуцированными по модулю коэффициентами. Основная идея:
X = |AB|_m = |(A₀*2⁰ + A₁*2¹+ ... + A_k*2^k)*(B₀*2⁰ + B₁*2¹+ ... + B_k*2^k)|_m = |(A₀*B₀*2⁰⁺⁰ + A₀*B₁*2⁰⁺¹ + ... + A_k*B_k*2^k+k)|_m