Verilog generator for RNS adder based on positional codes method

Select module:

Select number of inputs:

Structurally-hierarchical implementation:

module F_1_6 (x1_1, x2_1, x1_2, x2_2, out);
	input x1_1, x2_1, x1_2, x2_2;
	output reg out;
	wire [2:0] sum;

assign sum = 1*x1_1 + 2*x2_1 + 1*x1_2 + 2*x2_2;

always @(*)
	begin
	  if (sum == 1)
		out = 1;
	  else
		out = 0;
	end
endmodule

module F_4_6 (x1_1, x2_1, x1_2, x2_2, out);
	input x1_1, x2_1, x1_2, x2_2;
	output reg out;
	wire [2:0] sum;

assign sum = 1*x1_1 + 2*x2_1 + 1*x1_2 + 2*x2_2;

always @(*)
	begin
	  if (sum == 4)
		out = 1;
	  else
		out = 0;
	end
endmodule

module F_2_6 (x1_1, x2_1, x1_2, x2_2, out);
	input x1_1, x2_1, x1_2, x2_2;
	output reg out;
	wire [2:0] sum;

assign sum = 1*x1_1 + 2*x2_1 + 1*x1_2 + 2*x2_2;

always @(*)
	begin
	  if (sum == 2)
		out = 1;
	  else
		out = 0;
	end
endmodule

module adder (x1, x2, out);
	input [1:0] x1, x2;
	output [1:0] out;
	wire F_1, F_4, F_2;

F_1_6 (x1[0], x1[1], x2[0], x2[1], F_1);
	F_4_6 (x1[0], x1[1], x2[0], x2[1], F_4);
	F_2_6 (x1[0], x1[1], x2[0], x2[1], F_2);

assign out[0] = F_1 | F_4;
	assign out[1] = F_2;
endmodule

Test Bench:

Principles of the method:

More details in Russian here