Генератор Verilog для сумматора по произвольному простому модулю
Выберите простой модуль:
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Разрядность модуля: 5
Тип модуля: модуль специального вида 2
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Verilog описание сумматора Дима:
// Sum modulo (2^5 - 1) = 31 module sum_modulo_31 (A, B, S); input [4:0] A; input [4:0] B; output[4:0] S; wire [4:0] G; wire [4:0] P; wire [4:0] C; assign G[0] = A[0]&B[0]; assign G[1] = A[1]&B[1]; assign G[2] = A[2]&B[2]; assign G[3] = A[3]&B[3]; assign G[4] = A[4]&B[4]; assign P[0] = A[0]^B[0]; assign P[1] = A[1]^B[1]; assign P[2] = A[2]^B[2]; assign P[3] = A[3]^B[3]; assign P[4] = A[4]^B[4]; assign C[0] = G[0] | G[4]&P[0] | G[3]&P[0]&P[4] | G[2]&P[0]&P[4]&P[3] | G[1]&P[0]&P[4]&P[3]&P[2]; assign C[1] = G[1] | G[0]&P[1] | G[4]&P[1]&P[0] | G[3]&P[1]&P[0]&P[4] | G[2]&P[1]&P[0]&P[4]&P[3]; assign C[2] = G[2] | G[1]&P[2] | G[0]&P[2]&P[1] | G[4]&P[2]&P[1]&P[0] | G[3]&P[2]&P[1]&P[0]&P[4]; assign C[3] = G[3] | G[2]&P[3] | G[1]&P[3]&P[2] | G[0]&P[3]&P[2]&P[1] | G[4]&P[3]&P[2]&P[1]&P[0]; assign C[4] = G[4] | G[3]&P[4] | G[2]&P[4]&P[3] | G[1]&P[4]&P[3]&P[2] | G[0]&P[4]&P[3]&P[2]&P[1]; assign S[0] = (P[0]&&(~P[4:0]))^C[4]; assign S[1] = (P[1]&&(~P[4:0]))^C[0]; assign S[2] = (P[2]&&(~P[4:0]))^C[1]; assign S[3] = (P[3]&&(~P[4:0]))^C[2]; assign S[4] = (P[4]&&(~P[4:0]))^C[3]; endmodule
Verilog описание сумматора Рома:
// Sum modulo (2^5 - 1) = 31 module sum_modulo_31 (in1, in2, out); input [4:0] in1; input [4:0] in2; output reg [4:0] out; wire [5:0] data; wire [5:0] data2; assign data = in1 + in2; assign data2 = in1 + in2 + 1; always @(*) begin if (data2[5] == 1) out <= data2[4:0]; else out <= data[4:0]; end endmodule
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