Генератор Verilog для теоретико-числового БПФ

Выберите модуль (от 2 до 1000):

Выберите длину преобразования (от 4 до 1024):

Обратный FFT:

module manager_257 (stg1_out, stg2_out, stg3_out, stg4_out, stg5_out, stg6_out, in_count, clk);
	parameter WIDTH=9; 
	input                  clk;
	input [6:0]            in_count;	
	output reg [WIDTH-1:0] stg1_out, stg2_out, stg3_out, stg4_out, stg5_out, stg6_out; 
 
 
	always @ (posedge clk) 
	begin  
	//koeff on 1-st stage 
	case(in_count[6:0])
		127: stg1_out<= 0; 
		0: stg1_out<= 2; 
		1: stg1_out<= 4; 
		2: stg1_out<= 6; 
		3: stg1_out<= 8; 
		4: stg1_out<= 10; 
		5: stg1_out<= 12; 
		6: stg1_out<= 14; 
		7: stg1_out<= 16; 
		8: stg1_out<= 18; 
		9: stg1_out<= 20; 
		10: stg1_out<= 22; 
		11: stg1_out<= 24; 
		12: stg1_out<= 26; 
		13: stg1_out<= 28; 
		14: stg1_out<= 30; 
		15: stg1_out<= 32; 
		16: stg1_out<= 34; 
		17: stg1_out<= 36; 
		18: stg1_out<= 38; 
		19: stg1_out<= 40; 
		20: stg1_out<= 42; 
		21: stg1_out<= 44; 
		22: stg1_out<= 46; 
		23: stg1_out<= 48; 
		24: stg1_out<= 50; 
		25: stg1_out<= 52; 
		26: stg1_out<= 54; 
		27: stg1_out<= 56; 
		28: stg1_out<= 58; 
		29: stg1_out<= 60; 
		30: stg1_out<= 62; 
		31: stg1_out<= 64; 
		32: stg1_out<= 66; 
		33: stg1_out<= 68; 
		34: stg1_out<= 70; 
		35: stg1_out<= 72; 
		36: stg1_out<= 74; 
		37: stg1_out<= 76; 
		38: stg1_out<= 78; 
		39: stg1_out<= 80; 
		40: stg1_out<= 82; 
		41: stg1_out<= 84; 
		42: stg1_out<= 86; 
		43: stg1_out<= 88; 
		44: stg1_out<= 90; 
		45: stg1_out<= 92; 
		46: stg1_out<= 94; 
		47: stg1_out<= 96; 
		48: stg1_out<= 98; 
		49: stg1_out<= 100; 
		50: stg1_out<= 102; 
		51: stg1_out<= 104; 
		52: stg1_out<= 106; 
		53: stg1_out<= 108; 
		54: stg1_out<= 110; 
		55: stg1_out<= 112; 
		56: stg1_out<= 114; 
		57: stg1_out<= 116; 
		58: stg1_out<= 118; 
		59: stg1_out<= 120; 
		60: stg1_out<= 122; 
		61: stg1_out<= 124; 
		62: stg1_out<= 126; 
		63: stg1_out<= 0;
		64: stg1_out<= 0;
		65: stg1_out<= 0;
		66: stg1_out<= 0;
		67: stg1_out<= 0;
		68: stg1_out<= 0;
		69: stg1_out<= 0;
		70: stg1_out<= 0;
		71: stg1_out<= 0;
		72: stg1_out<= 0;
		73: stg1_out<= 0;
		74: stg1_out<= 0;
		75: stg1_out<= 0;
		76: stg1_out<= 0;
		77: stg1_out<= 0;
		78: stg1_out<= 0;
		79: stg1_out<= 0;
		80: stg1_out<= 0;
		81: stg1_out<= 0;
		82: stg1_out<= 0;
		83: stg1_out<= 0;
		84: stg1_out<= 0;
		85: stg1_out<= 0;
		86: stg1_out<= 0;
		87: stg1_out<= 0;
		88: stg1_out<= 0;
		89: stg1_out<= 0;
		90: stg1_out<= 0;
		91: stg1_out<= 0;
		92: stg1_out<= 0;
		93: stg1_out<= 0;
		94: stg1_out<= 0;
		95: stg1_out<= 0;
		96: stg1_out<= 0;
		97: stg1_out<= 0;
		98: stg1_out<= 0;
		99: stg1_out<= 0;
		100: stg1_out<= 0;
		101: stg1_out<= 0;
		102: stg1_out<= 0;
		103: stg1_out<= 0;
		104: stg1_out<= 0;
		105: stg1_out<= 0;
		106: stg1_out<= 0;
		107: stg1_out<= 0;
		108: stg1_out<= 0;
		109: stg1_out<= 0;
		110: stg1_out<= 0;
		111: stg1_out<= 0;
		112: stg1_out<= 0;
		113: stg1_out<= 0;
		114: stg1_out<= 0;
		115: stg1_out<= 0;
		116: stg1_out<= 0;
		117: stg1_out<= 0;
		118: stg1_out<= 0;
		119: stg1_out<= 0;
		120: stg1_out<= 0;
		121: stg1_out<= 0;
		122: stg1_out<= 0;
		123: stg1_out<= 0;
		124: stg1_out<= 0;
		125: stg1_out<= 0;
		126: stg1_out<= 0;
	endcase 
	//koeff on 2-st stage 
	case(in_count[5:0])
		63: stg2_out<= 0; 
		0: stg2_out<= 4; 
		1: stg2_out<= 8; 
		2: stg2_out<= 12; 
		3: stg2_out<= 16; 
		4: stg2_out<= 20; 
		5: stg2_out<= 24; 
		6: stg2_out<= 28; 
		7: stg2_out<= 32; 
		8: stg2_out<= 36; 
		9: stg2_out<= 40; 
		10: stg2_out<= 44; 
		11: stg2_out<= 48; 
		12: stg2_out<= 52; 
		13: stg2_out<= 56; 
		14: stg2_out<= 60; 
		15: stg2_out<= 64; 
		16: stg2_out<= 68; 
		17: stg2_out<= 72; 
		18: stg2_out<= 76; 
		19: stg2_out<= 80; 
		20: stg2_out<= 84; 
		21: stg2_out<= 88; 
		22: stg2_out<= 92; 
		23: stg2_out<= 96; 
		24: stg2_out<= 100; 
		25: stg2_out<= 104; 
		26: stg2_out<= 108; 
		27: stg2_out<= 112; 
		28: stg2_out<= 116; 
		29: stg2_out<= 120; 
		30: stg2_out<= 124; 
		31: stg2_out<= 0;
		32: stg2_out<= 0;
		33: stg2_out<= 0;
		34: stg2_out<= 0;
		35: stg2_out<= 0;
		36: stg2_out<= 0;
		37: stg2_out<= 0;
		38: stg2_out<= 0;
		39: stg2_out<= 0;
		40: stg2_out<= 0;
		41: stg2_out<= 0;
		42: stg2_out<= 0;
		43: stg2_out<= 0;
		44: stg2_out<= 0;
		45: stg2_out<= 0;
		46: stg2_out<= 0;
		47: stg2_out<= 0;
		48: stg2_out<= 0;
		49: stg2_out<= 0;
		50: stg2_out<= 0;
		51: stg2_out<= 0;
		52: stg2_out<= 0;
		53: stg2_out<= 0;
		54: stg2_out<= 0;
		55: stg2_out<= 0;
		56: stg2_out<= 0;
		57: stg2_out<= 0;
		58: stg2_out<= 0;
		59: stg2_out<= 0;
		60: stg2_out<= 0;
		61: stg2_out<= 0;
		62: stg2_out<= 0;
	endcase 
	//koeff on 3-st stage 
	case(in_count[4:0])
		31: stg3_out<= 0; 
		0: stg3_out<= 8; 
		1: stg3_out<= 16; 
		2: stg3_out<= 24; 
		3: stg3_out<= 32; 
		4: stg3_out<= 40; 
		5: stg3_out<= 48; 
		6: stg3_out<= 56; 
		7: stg3_out<= 64; 
		8: stg3_out<= 72; 
		9: stg3_out<= 80; 
		10: stg3_out<= 88; 
		11: stg3_out<= 96; 
		12: stg3_out<= 104; 
		13: stg3_out<= 112; 
		14: stg3_out<= 120; 
		15: stg3_out<= 0;
		16: stg3_out<= 0;
		17: stg3_out<= 0;
		18: stg3_out<= 0;
		19: stg3_out<= 0;
		20: stg3_out<= 0;
		21: stg3_out<= 0;
		22: stg3_out<= 0;
		23: stg3_out<= 0;
		24: stg3_out<= 0;
		25: stg3_out<= 0;
		26: stg3_out<= 0;
		27: stg3_out<= 0;
		28: stg3_out<= 0;
		29: stg3_out<= 0;
		30: stg3_out<= 0;
	endcase 
	//koeff on 4-st stage 
	case(in_count[3:0])
		15: stg4_out<= 0; 
		0: stg4_out<= 16; 
		1: stg4_out<= 32; 
		2: stg4_out<= 48; 
		3: stg4_out<= 64; 
		4: stg4_out<= 80; 
		5: stg4_out<= 96; 
		6: stg4_out<= 112; 
		7: stg4_out<= 0;
		8: stg4_out<= 0;
		9: stg4_out<= 0;
		10: stg4_out<= 0;
		11: stg4_out<= 0;
		12: stg4_out<= 0;
		13: stg4_out<= 0;
		14: stg4_out<= 0;
	endcase 
	//koeff on 5-st stage 
	case(in_count[2:0])
		7: stg5_out<= 0; 
		0: stg5_out<= 32; 
		1: stg5_out<= 64; 
		2: stg5_out<= 96; 
		3: stg5_out<= 0;
		4: stg5_out<= 0;
		5: stg5_out<= 0;
		6: stg5_out<= 0;
	endcase 
	//koeff on 6-st stage 
	case(in_count[1:0])
		3: stg6_out<= 0; 
		0: stg6_out<= 64; 
		1: stg6_out<= 0;
		2: stg6_out<= 0;
	endcase 
 
	end
 
endmodule

module mux (res, dataa, datab, sel);
	parameter WIDTH=9;

input   [WIDTH-1:0] dataa;
	input   [WIDTH-1:0] datab;
	input                 sel;
	output reg  [WIDTH-1:0]   res;
	
	always @ (sel or dataa or datab)
	begin
	case(sel)
		1'b0: res = datab;
		1'b1: res = dataa;
	endcase
	end
endmodule

module shift_reg_64 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:63] ;

// Block Statements
  always @( posedge clk or posedge reset)
    begin: Delay_Pipeline_process
      if (reset == 1'b1) begin
        delay_pipeline[0] <= 0;
        delay_pipeline[1] <= 0;
        delay_pipeline[2] <= 0;
        delay_pipeline[3] <= 0;
        delay_pipeline[4] <= 0;
        delay_pipeline[5] <= 0;
        delay_pipeline[6] <= 0;
        delay_pipeline[7] <= 0;
        delay_pipeline[8] <= 0;
        delay_pipeline[9] <= 0;
        delay_pipeline[10] <= 0;
        delay_pipeline[11] <= 0;
        delay_pipeline[12] <= 0;
        delay_pipeline[13] <= 0;
        delay_pipeline[14] <= 0;
        delay_pipeline[15] <= 0;
        delay_pipeline[16] <= 0;
        delay_pipeline[17] <= 0;
        delay_pipeline[18] <= 0;
        delay_pipeline[19] <= 0;
        delay_pipeline[20] <= 0;
        delay_pipeline[21] <= 0;
        delay_pipeline[22] <= 0;
        delay_pipeline[23] <= 0;
        delay_pipeline[24] <= 0;
        delay_pipeline[25] <= 0;
        delay_pipeline[26] <= 0;
        delay_pipeline[27] <= 0;
        delay_pipeline[28] <= 0;
        delay_pipeline[29] <= 0;
        delay_pipeline[30] <= 0;
        delay_pipeline[31] <= 0;
        delay_pipeline[32] <= 0;
        delay_pipeline[33] <= 0;
        delay_pipeline[34] <= 0;
        delay_pipeline[35] <= 0;
        delay_pipeline[36] <= 0;
        delay_pipeline[37] <= 0;
        delay_pipeline[38] <= 0;
        delay_pipeline[39] <= 0;
        delay_pipeline[40] <= 0;
        delay_pipeline[41] <= 0;
        delay_pipeline[42] <= 0;
        delay_pipeline[43] <= 0;
        delay_pipeline[44] <= 0;
        delay_pipeline[45] <= 0;
        delay_pipeline[46] <= 0;
        delay_pipeline[47] <= 0;
        delay_pipeline[48] <= 0;
        delay_pipeline[49] <= 0;
        delay_pipeline[50] <= 0;
        delay_pipeline[51] <= 0;
        delay_pipeline[52] <= 0;
        delay_pipeline[53] <= 0;
        delay_pipeline[54] <= 0;
        delay_pipeline[55] <= 0;
        delay_pipeline[56] <= 0;
        delay_pipeline[57] <= 0;
        delay_pipeline[58] <= 0;
        delay_pipeline[59] <= 0;
        delay_pipeline[60] <= 0;
        delay_pipeline[61] <= 0;
        delay_pipeline[62] <= 0;
        delay_pipeline[63] <= 0;
        end
      else begin
        if (clk_enable == 1'b1) begin
          delay_pipeline[0] <= datain;
          delay_pipeline[1] <= delay_pipeline[0];
          delay_pipeline[2] <= delay_pipeline[1];
          delay_pipeline[3] <= delay_pipeline[2];
          delay_pipeline[4] <= delay_pipeline[3];
          delay_pipeline[5] <= delay_pipeline[4];
          delay_pipeline[6] <= delay_pipeline[5];
          delay_pipeline[7] <= delay_pipeline[6];
          delay_pipeline[8] <= delay_pipeline[7];
          delay_pipeline[9] <= delay_pipeline[8];
          delay_pipeline[10] <= delay_pipeline[9];
          delay_pipeline[11] <= delay_pipeline[10];
          delay_pipeline[12] <= delay_pipeline[11];
          delay_pipeline[13] <= delay_pipeline[12];
          delay_pipeline[14] <= delay_pipeline[13];
          delay_pipeline[15] <= delay_pipeline[14];
          delay_pipeline[16] <= delay_pipeline[15];
          delay_pipeline[17] <= delay_pipeline[16];
          delay_pipeline[18] <= delay_pipeline[17];
          delay_pipeline[19] <= delay_pipeline[18];
          delay_pipeline[20] <= delay_pipeline[19];
          delay_pipeline[21] <= delay_pipeline[20];
          delay_pipeline[22] <= delay_pipeline[21];
          delay_pipeline[23] <= delay_pipeline[22];
          delay_pipeline[24] <= delay_pipeline[23];
          delay_pipeline[25] <= delay_pipeline[24];
          delay_pipeline[26] <= delay_pipeline[25];
          delay_pipeline[27] <= delay_pipeline[26];
          delay_pipeline[28] <= delay_pipeline[27];
          delay_pipeline[29] <= delay_pipeline[28];
          delay_pipeline[30] <= delay_pipeline[29];
          delay_pipeline[31] <= delay_pipeline[30];
          delay_pipeline[32] <= delay_pipeline[31];
          delay_pipeline[33] <= delay_pipeline[32];
          delay_pipeline[34] <= delay_pipeline[33];
          delay_pipeline[35] <= delay_pipeline[34];
          delay_pipeline[36] <= delay_pipeline[35];
          delay_pipeline[37] <= delay_pipeline[36];
          delay_pipeline[38] <= delay_pipeline[37];
          delay_pipeline[39] <= delay_pipeline[38];
          delay_pipeline[40] <= delay_pipeline[39];
          delay_pipeline[41] <= delay_pipeline[40];
          delay_pipeline[42] <= delay_pipeline[41];
          delay_pipeline[43] <= delay_pipeline[42];
          delay_pipeline[44] <= delay_pipeline[43];
          delay_pipeline[45] <= delay_pipeline[44];
          delay_pipeline[46] <= delay_pipeline[45];
          delay_pipeline[47] <= delay_pipeline[46];
          delay_pipeline[48] <= delay_pipeline[47];
          delay_pipeline[49] <= delay_pipeline[48];
          delay_pipeline[50] <= delay_pipeline[49];
          delay_pipeline[51] <= delay_pipeline[50];
          delay_pipeline[52] <= delay_pipeline[51];
          delay_pipeline[53] <= delay_pipeline[52];
          delay_pipeline[54] <= delay_pipeline[53];
          delay_pipeline[55] <= delay_pipeline[54];
          delay_pipeline[56] <= delay_pipeline[55];
          delay_pipeline[57] <= delay_pipeline[56];
          delay_pipeline[58] <= delay_pipeline[57];
          delay_pipeline[59] <= delay_pipeline[58];
          delay_pipeline[60] <= delay_pipeline[59];
          delay_pipeline[61] <= delay_pipeline[60];
          delay_pipeline[62] <= delay_pipeline[61];
          delay_pipeline[63] <= delay_pipeline[62];
        end
      end
    end // Delay_Pipeline_process
assign dataout = delay_pipeline[63]; // connection to dataout
endmodule

module shift_reg_32 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:31] ;

module shift_reg_16 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:15] ;

module shift_reg_8 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:7] ;

module shift_reg_4 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:3] ;

module shift_reg_2 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:1] ;

// Block Statements
  always @( posedge clk or posedge reset)
    begin: Delay_Pipeline_process
      if (reset == 1'b1) begin
        delay_pipeline[0] <= 0;
        delay_pipeline[1] <= 0;
        end
      else begin
        if (clk_enable == 1'b1) begin
          delay_pipeline[0] <= datain;
          delay_pipeline[1] <= delay_pipeline[0];
        end
      end
    end // Delay_Pipeline_process
assign dataout = delay_pipeline[1]; // connection to dataout
endmodule

module shift_reg_1 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=9;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline [0:0] ;

// Block Statements
  always @( posedge clk or posedge reset)
    begin: Delay_Pipeline_process
      if (reset == 1'b1) begin
        delay_pipeline[0] <= 0;
        end
      else begin
        if (clk_enable == 1'b1) begin
          delay_pipeline[0] <= datain;
        end
      end
    end // Delay_Pipeline_process
assign dataout = delay_pipeline[0]; // connection to dataout
endmodule

module Ind_adder257 (data_out, data_A, data_B);
	parameter p = 257;
	parameter NBRB =9;

output reg		[NBRB-1:0]	data_out;
	input  			[NBRB-1:0]	data_A, data_B;
	always @(data_A or data_B)
	begin
		if((data_A == 511) || (data_B == 511) )
			begin
				data_out <= 511;
			end
		else
			begin
				if ({1'b0,data_A} + {1'b0,data_B} < p - 1) data_out <= {1'b0,data_A} + {1'b0,data_B};
				else data_out <= {1'b0,data_A} + {1'b0,data_B} - (p - 1);
			end
	end
endmodule

module Mult_257 (Out, A, gamma);
	parameter WIDTH = 9;
	output	[WIDTH-1:0]	Out;
	input	[WIDTH-1:0]	A, gamma;
	wire [WIDTH-1:0] Index_out, Adder_out;

Index_ROM_257			#(WIDTH)		in1		(Index_out, A);
	Ind_adder257				#(257, WIDTH)	add1	(Adder_out, Index_out, gamma);
	Vichet_ROM_257			#(WIDTH)		vic1	(Out, Adder_out);

endmodule

module butterfly_257 (A, B, add, sub);
  input   [8:0] A, B; 
  output reg [8:0] add, sub; 
  
  
		always @(A or B) 
			begin 
					if ({1'b0, A} + {1'b0, B} < 257) add <= {1'b0, A} + {1'b0, B};
					else add <= {1'b0, A} + {1'b0, B} - (257); 
					
					if ({1'b0, A} > {1'b0, B}) sub <= {1'b0, B} - {1'b0, A} + (257); 
					else sub <= {1'b0, B} - {1'b0, A}; 
			end
endmodule

module stage_257_64 (clk, clk_enable, reset, In, Out, sel, gamma);