Генератор Verilog конвеерного FIR-фильтра на базе системы остаточных классов

* - Если данные выйдут за 32 бита, корректность пока не гарантируется
Размерность входных данных (в битах): 3
Коэффициенты фильтра: 34 65 37 87 12 64 76 12
Набор простых чисел, найденный для заданного фильтра: 97 113
module mod_conv_97 (clk, reset, In, Out, clk_enable);

	input   clk; 
	input   reset; 
	input   clk_enable; 
	input   [6:0] In; 
	output  [6:0] Out; 

    
	wire [6:0] fwd_Out, Mult_out, zerout, inv_Out;
	reg  [3:0] count;
	reg reset2, reset1;

	zero_pad #(7) zero (zerout, In, clk, reset, clk_enable);	
	fft_97 stg1 (clk, clk_enable, reset1, zerout, fwd_Out);
	mult_modulo_97 mlt ({count[0], count[1], count[2], count[3]}, fwd_Out, Mult_out, clk);
	i_fft_97 stg2 (clk, clk_enable, reset2, Mult_out, inv_Out);
	overlap_add_97 add (Out, inv_Out, clk, reset, clk_enable);


	// Sequential blocks that have purpose of !!!MANAGING CLOCKS!!!	
	always @ (posedge clk or posedge reset1)
	begin
		if (reset1)
			count <= 1;
		else 
			count <= count + 1;
	end


	always @ (posedge clk)
	begin
		if (count == 0)	reset2 <= 0;
		if (reset == 0) reset1 <= 0;
		if (reset == 1) begin reset1 <= 1; reset2 <= 1; end
	end
endmodule

module overlap_add_97 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input  clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg clk_2;
	wire [WIDTH-1:0] shift1_out, adder_out;
	
	
	// Block Statements
	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			clk_2 <= 0;
		else 
			clk_2 <= ~clk_2;
	end 


	shift_reg_8 #(WIDTH) shift1 (shift1_out, datain, clk, reset, clk_enable);
	mod_adder #(97, 7) add (adder_out, shift1_out, datain);
	slow_down_8 #(WIDTH) slow (dataout, adder_out, clk, clk_2, reset, clk_enable);

endmodule

module Ind_adder97 (data_out, data_A, data_B);
	parameter p = 97;
	parameter NBRB =7;

	output reg [NBRB-1:0] data_out;
	input [NBRB-1:0] data_A, data_B;
	always @(data_A or data_B)
	begin
		if((data_A == 127) || (data_B == 127) )
			begin
				data_out <= 127;
			end
		else
			begin
				if ({1'b0,data_A} + {1'b0,data_B} < p - 1) data_out <= {1'b0,data_A} + {1'b0,data_B};
				else data_out <= {1'b0,data_A} + {1'b0,data_B} - (p - 1);
			end
	end
endmodule

module Mult_97 (Out, A, gamma);
	parameter WIDTH = 7;
	output	[WIDTH-1:0]	Out;
	input	[WIDTH-1:0]	A, gamma;
	wire [WIDTH-1:0] Index_out, Adder_out;

	Index_ROM_97 #(WIDTH) in1 (Index_out, A);
	Ind_adder97 #(97, WIDTH) add1 (Adder_out, Index_out, gamma);
	Vichet_ROM_97 #(WIDTH) vic1 (Out, Adder_out);

endmodule

module butterfly_97 (A, B, add, sub);
	input   [6:0] A, B; 
	output reg [6:0] add, sub; 


	always @(A or B) 
	begin 
		if ({1'b0, A} + {1'b0, B} < 97) add <= {1'b0, A} + {1'b0, B};
		else add <= {1'b0, A} + {1'b0, B} - (97); 

		if ({1'b0, A} > {1'b0, B}) sub <= {1'b0, B} - {1'b0, A} + (97); 
		else sub <= {1'b0, B} - {1'b0, A}; 
	end 
endmodule

module Index_ROM_97 (data_out, data_x);
	parameter NBRB = 7;
	output reg	[NBRB-1:0]	data_out;
	input 		[NBRB-1:0]	data_x;

	always @(data_x)
	begin
		case(data_x)
		0: data_out <= 127;	
		1: data_out <= 0;	
		2: data_out <= 34;	
		3: data_out <= 70;	
		4: data_out <= 68;	
		5: data_out <= 1;	
		6: data_out <= 8;	
		7: data_out <= 31;	
		8: data_out <= 6;	
		9: data_out <= 44;	
		10: data_out <= 35;	
		11: data_out <= 86;	
		12: data_out <= 42;	
		13: data_out <= 25;	
		14: data_out <= 65;	
		15: data_out <= 71;	
		16: data_out <= 40;	
		17: data_out <= 89;	
		18: data_out <= 78;	
		19: data_out <= 81;	
		20: data_out <= 69;	
		21: data_out <= 5;	
		22: data_out <= 24;	
		23: data_out <= 77;	
		24: data_out <= 76;	
		25: data_out <= 2;	
		26: data_out <= 59;	
		27: data_out <= 18;	
		28: data_out <= 3;	
		29: data_out <= 13;	
		30: data_out <= 9;	
		31: data_out <= 46;	
		32: data_out <= 74;	
		33: data_out <= 60;	
		34: data_out <= 27;	
		35: data_out <= 32;	
		36: data_out <= 16;	
		37: data_out <= 91;	
		38: data_out <= 19;	
		39: data_out <= 95;	
		40: data_out <= 7;	
		41: data_out <= 85;	
		42: data_out <= 39;	
		43: data_out <= 4;	
		44: data_out <= 58;	
		45: data_out <= 45;	
		46: data_out <= 15;	
		47: data_out <= 84;	
		48: data_out <= 14;	
		49: data_out <= 62;	
		50: data_out <= 36;	
		51: data_out <= 63;	
		52: data_out <= 93;	
		53: data_out <= 10;	
		54: data_out <= 52;	
		55: data_out <= 87;	
		56: data_out <= 37;	
		57: data_out <= 55;	
		58: data_out <= 47;	
		59: data_out <= 67;	
		60: data_out <= 43;	
		61: data_out <= 64;	
		62: data_out <= 80;	
		63: data_out <= 75;	
		64: data_out <= 12;	
		65: data_out <= 26;	
		66: data_out <= 94;	
		67: data_out <= 57;	
		68: data_out <= 61;	
		69: data_out <= 51;	
		70: data_out <= 66;	
		71: data_out <= 11;	
		72: data_out <= 50;	
		73: data_out <= 28;	
		74: data_out <= 29;	
		75: data_out <= 72;	
		76: data_out <= 53;	
		77: data_out <= 21;	
		78: data_out <= 33;	
		79: data_out <= 30;	
		80: data_out <= 41;	
		81: data_out <= 88;	
		82: data_out <= 23;	
		83: data_out <= 17;	
		84: data_out <= 73;	
		85: data_out <= 90;	
		86: data_out <= 38;	
		87: data_out <= 83;	
		88: data_out <= 92;	
		89: data_out <= 54;	
		90: data_out <= 79;	
		91: data_out <= 56;	
		92: data_out <= 49;	
		93: data_out <= 20;	
		94: data_out <= 22;	
		95: data_out <= 82;	
		96: data_out <= 48;	
		default data_out <= 127;
		endcase
	end
endmodule

module Vichet_ROM_97 (data_out, data_x);
	parameter NBRB = 7;
	output reg	[NBRB-1:0]	data_out;
	input 		[NBRB-1:0]	data_x;

	always @(data_x)
	begin	
		case(data_x)
			0: data_out <= 1;	
		1: data_out <= 5;	
		2: data_out <= 25;	
		3: data_out <= 28;	
		4: data_out <= 43;	
		5: data_out <= 21;	
		6: data_out <= 8;	
		7: data_out <= 40;	
		8: data_out <= 6;	
		9: data_out <= 30;	
		10: data_out <= 53;	
		11: data_out <= 71;	
		12: data_out <= 64;	
		13: data_out <= 29;	
		14: data_out <= 48;	
		15: data_out <= 46;	
		16: data_out <= 36;	
		17: data_out <= 83;	
		18: data_out <= 27;	
		19: data_out <= 38;	
		20: data_out <= 93;	
		21: data_out <= 77;	
		22: data_out <= 94;	
		23: data_out <= 82;	
		24: data_out <= 22;	
		25: data_out <= 13;	
		26: data_out <= 65;	
		27: data_out <= 34;	
		28: data_out <= 73;	
		29: data_out <= 74;	
		30: data_out <= 79;	
		31: data_out <= 7;	
		32: data_out <= 35;	
		33: data_out <= 78;	
		34: data_out <= 2;	
		35: data_out <= 10;	
		36: data_out <= 50;	
		37: data_out <= 56;	
		38: data_out <= 86;	
		39: data_out <= 42;	
		40: data_out <= 16;	
		41: data_out <= 80;	
		42: data_out <= 12;	
		43: data_out <= 60;	
		44: data_out <= 9;	
		45: data_out <= 45;	
		46: data_out <= 31;	
		47: data_out <= 58;	
		48: data_out <= 96;	
		49: data_out <= 92;	
		50: data_out <= 72;	
		51: data_out <= 69;	
		52: data_out <= 54;	
		53: data_out <= 76;	
		54: data_out <= 89;	
		55: data_out <= 57;	
		56: data_out <= 91;	
		57: data_out <= 67;	
		58: data_out <= 44;	
		59: data_out <= 26;	
		60: data_out <= 33;	
		61: data_out <= 68;	
		62: data_out <= 49;	
		63: data_out <= 51;	
		64: data_out <= 61;	
		65: data_out <= 14;	
		66: data_out <= 70;	
		67: data_out <= 59;	
		68: data_out <= 4;	
		69: data_out <= 20;	
		70: data_out <= 3;	
		71: data_out <= 15;	
		72: data_out <= 75;	
		73: data_out <= 84;	
		74: data_out <= 32;	
		75: data_out <= 63;	
		76: data_out <= 24;	
		77: data_out <= 23;	
		78: data_out <= 18;	
		79: data_out <= 90;	
		80: data_out <= 62;	
		81: data_out <= 19;	
		82: data_out <= 95;	
		83: data_out <= 87;	
		84: data_out <= 47;	
		85: data_out <= 41;	
		86: data_out <= 11;	
		87: data_out <= 55;	
		88: data_out <= 81;	
		89: data_out <= 17;	
		90: data_out <= 85;	
		91: data_out <= 37;	
		92: data_out <= 88;	
		93: data_out <= 52;	
		94: data_out <= 66;	
		95: data_out <= 39;	
		default data_out <= 0;
		endcase
	end
endmodule

module manager_97 (stg1_out, stg2_out, stg3_out, in_count, clk);
	parameter WIDTH=7; 
	input                  clk;
	input [3:0]            in_count;	
	output reg [WIDTH-1:0] stg1_out, stg2_out, stg3_out; 
 
 
	always @ (posedge clk)
	begin
	//koeff on 1-st stage 
	case(in_count[3:0]) 	
	    15: begin 
	    stg1_out<= 0; 
		end
	    0: begin 
	    stg1_out<= 6; 
		end
	    1: begin 
	    stg1_out<= 12; 
		end
	    2: begin 
	    stg1_out<= 18; 
		end
	    3: begin 
	    stg1_out<= 24; 
		end
	    4: begin 
	    stg1_out<= 30; 
		end
	    5: begin 
	    stg1_out<= 36; 
		end
	    6: begin 
	    stg1_out<= 42; 
		end
	    7: begin 
	    stg1_out<= 0; 
		end
	    8: begin 
	    stg1_out<= 0; 
		end
	    9: begin 
	    stg1_out<= 0; 
		end
	    10: begin 
	    stg1_out<= 0; 
		end
	    11: begin 
	    stg1_out<= 0; 
		end
	    12: begin 
	    stg1_out<= 0; 
		end
	    13: begin 
	    stg1_out<= 0; 
		end
	    14: begin 
	    stg1_out<= 0; 
		end
	endcase
	//koeff on 2-st stage 
	case(in_count[2:0]) 	
	    7: begin 
	    stg2_out<= 0; 
		end
	    0: begin 
	    stg2_out<= 12; 
		end
	    1: begin 
	    stg2_out<= 24; 
		end
	    2: begin 
	    stg2_out<= 36; 
		end
	    3: begin 
	    stg2_out<= 0; 
		end
	    4: begin 
	    stg2_out<= 0; 
		end
	    5: begin 
	    stg2_out<= 0; 
		end
	    6: begin 
	    stg2_out<= 0; 
		end
	endcase
	//koeff on 3-st stage 
	case(in_count[1:0]) 	
	    3: begin 
	    stg3_out<= 0; 
		end
	    0: begin 
	    stg3_out<= 24; 
		end
	    1: begin 
	    stg3_out<= 0; 
		end
	    2: begin 
	    stg3_out<= 0; 
		end
	endcase

	end

endmodule

module stage_97_8 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mux_Out;


	butterfly_97 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (mux_Out, butt_add, shiftout, sel); 
	shift_reg_8 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_97 mult (Out, mux_Out, gamma);     
	//assign Out = mux_Out; 

endmodule

module stage_97_4 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mux_Out;


	butterfly_97 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (mux_Out, butt_add, shiftout, sel); 
	shift_reg_4 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_97 mult (Out, mux_Out, gamma);     
	//assign Out = mux_Out; 

endmodule

module stage_97_2 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mux_Out;


	butterfly_97 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (mux_Out, butt_add, shiftout, sel); 
	shift_reg_2 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_97 mult (Out, mux_Out, gamma);     
	//assign Out = mux_Out; 

endmodule

module stage_97_1 (clk, clk_enable, reset, In, Out, sel);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub;


	butterfly_97 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_1 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);


endmodule

module fft_97 (clk, clk_enable, reset, In, Out);

	input   clk; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 
	reg [3:0] count;

	wire [6:0] Stg1_out, Stg2_out, Stg3_out;
	wire [6:0] stg1_coeff, stg2_coeff, stg3_coeff;

	stage_97_8 stg1 (clk, clk_enable, reset, In, Stg1_out, count[3], stg1_coeff);
	stage_97_4 stg2 (clk, clk_enable, reset, Stg1_out, Stg2_out, count[2], stg2_coeff);
	stage_97_2 stg3 (clk, clk_enable, reset, Stg2_out, Stg3_out, count[1], stg3_coeff);
	stage_97_1 stg4 (clk, clk_enable, reset, Stg3_out, Out, count[0]);
	manager_97 mng  (stg1_coeff, stg2_coeff, stg3_coeff, count, clk);	


	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			count <= 0;
		else if (clk_enable == 1'b1)
			count <= count + 1;
	end
endmodule

module i_manager_97 (stg1_out, stg2_out, stg3_out, in_count, clk);
	parameter WIDTH=7; 
	input                  clk;
	input [3:0]            in_count;	
	output reg [WIDTH-1:0] stg1_out, stg2_out, stg3_out; 
 
 
	always @ (posedge clk) 
	begin  
	//koeff on 1-st stage 
	case(in_count[3:0]) 	
	    0: begin 
	    stg1_out<= 56; 
		end
	    15: begin 
	    stg1_out<= 50; 
		end
	    14: begin 
	    stg1_out<= 44; 
		end
	    13: begin 
	    stg1_out<= 38; 
		end
	    12: begin 
	    stg1_out<= 32; 
		end
	    11: begin 
	    stg1_out<= 26; 
		end
	    10: begin 
	    stg1_out<= 20; 
		end
	    9: begin 
	    stg1_out<= 14; 
		end
	    8: begin 
	    stg1_out<= 56; 
		end
	    7: begin 
	    stg1_out<= 56; 
		end
	    6: begin 
	    stg1_out<= 56; 
		end
	    5: begin 
	    stg1_out<= 56; 
		end
	    4: begin 
	    stg1_out<= 56; 
		end
	    3: begin 
	    stg1_out<= 56; 
		end
	    2: begin 
	    stg1_out<= 56; 
		end
	    1: begin 
	    stg1_out<= 56; 
		end
	endcase 

	//koeff on 2-st stage
	case(in_count[2:0])
	    0: begin 
	    stg2_out<= 0; 
		end
	    7: begin 
	    stg2_out<= 84; 
		end
	    6: begin 
	    stg2_out<= 72; 
		end
	    5: begin 
	    stg2_out<= 60; 
		end
	    4: begin 
	    stg2_out<= 0; 
		end
	    3: begin 
	    stg2_out<= 0; 
		end
	    2: begin 
	    stg2_out<= 0; 
		end
	    1: begin 
	    stg2_out<= 0; 
		end
	endcase

	//koeff on 3-st stage
	case(in_count[1:0])
	    0: begin 
	    stg3_out<= 0; 
		end
	    3: begin 
	    stg3_out<= 72; 
		end
	    2: begin 
	    stg3_out<= 0; 
		end
	    1: begin 
	    stg3_out<= 0; 
		end
	endcase

	end

endmodule

module i_stage_97_8 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mult_Out;


	butterfly_97 butt (mult_Out, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, mult_Out, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_8 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_97 mult (mult_Out, In, gamma);     
	//assign Out = mux_Out; 

endmodule

module i_stage_97_4 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mult_Out;


	butterfly_97 butt (mult_Out, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_4 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_97 mult (mult_Out, In, gamma);     
	//assign Out = mux_Out; 

endmodule

module i_stage_97_2 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mult_Out;


	butterfly_97 butt (mult_Out, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_2 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_97 mult (mult_Out, In, gamma);     
	//assign Out = mux_Out; 

endmodule

module i_stage_97_1 (clk, clk_enable, reset, In, Out, sel);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub;


	butterfly_97 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_1 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);


endmodule

module i_fft_97 (clk, clk_enable, reset, In, Out);

	input   clk; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 
	reg [3:0] count;

	wire [6:0] Stg1_out, Stg2_out, Stg3_out;
	wire [6:0] stg1_coeff, stg2_coeff, stg3_coeff;

	i_stage_97_1 stg1 (clk, clk_enable, reset, In, Stg1_out, count[0]);
	i_stage_97_2 stg2 (clk, clk_enable, reset, Stg1_out, Stg2_out, count[1], stg3_coeff);
	i_stage_97_4 stg3 (clk, clk_enable, reset, Stg2_out, Stg3_out, count[2], stg2_coeff);
	i_stage_97_8 stg4 (clk, clk_enable, reset, Stg3_out, Out, count[3], stg1_coeff);
	i_manager_97 mng  (stg1_coeff, stg2_coeff, stg3_coeff, count, clk);	


	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			count <= 14;
		else if (clk_enable == 1'b1)
			count <= count - 1;
	end
endmodule



module lut_for_filter_2_pow_0_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 96;
		1: out = 23;
		2: out = 84;
		3: out = 29;
		4: out = 48;
		5: out = 96;
		6: out = 59;
		7: out = 62;
		8: out = 69;
		9: out = 77;
		10: out = 4;
		11: out = 92;
		12: out = 86;
		13: out = 53;
		14: out = 38;
		15: out = 52;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_1_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 95;
		1: out = 46;
		2: out = 71;
		3: out = 58;
		4: out = 96;
		5: out = 95;
		6: out = 21;
		7: out = 27;
		8: out = 41;
		9: out = 57;
		10: out = 8;
		11: out = 87;
		12: out = 75;
		13: out = 9;
		14: out = 76;
		15: out = 7;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_2_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 93;
		1: out = 92;
		2: out = 45;
		3: out = 19;
		4: out = 95;
		5: out = 93;
		6: out = 42;
		7: out = 54;
		8: out = 82;
		9: out = 17;
		10: out = 16;
		11: out = 77;
		12: out = 53;
		13: out = 18;
		14: out = 55;
		15: out = 14;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_3_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 89;
		1: out = 87;
		2: out = 90;
		3: out = 38;
		4: out = 93;
		5: out = 89;
		6: out = 84;
		7: out = 11;
		8: out = 67;
		9: out = 34;
		10: out = 32;
		11: out = 57;
		12: out = 9;
		13: out = 36;
		14: out = 13;
		15: out = 28;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_4_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 81;
		1: out = 77;
		2: out = 83;
		3: out = 76;
		4: out = 89;
		5: out = 81;
		6: out = 71;
		7: out = 22;
		8: out = 37;
		9: out = 68;
		10: out = 64;
		11: out = 17;
		12: out = 18;
		13: out = 72;
		14: out = 26;
		15: out = 56;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_5_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 65;
		1: out = 57;
		2: out = 69;
		3: out = 55;
		4: out = 81;
		5: out = 65;
		6: out = 45;
		7: out = 44;
		8: out = 74;
		9: out = 39;
		10: out = 31;
		11: out = 34;
		12: out = 36;
		13: out = 47;
		14: out = 52;
		15: out = 15;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_6_97 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 33;
		1: out = 17;
		2: out = 41;
		3: out = 13;
		4: out = 65;
		5: out = 33;
		6: out = 90;
		7: out = 88;
		8: out = 51;
		9: out = 78;
		10: out = 62;
		11: out = 68;
		12: out = 72;
		13: out = 94;
		14: out = 7;
		15: out = 30;
		default: out = 0; 
	endcase 
endmodule

module mod_97_567_c (in, out, clk);
	input clk;
	input [9:0] in;
	output reg [6:0] out;
	always @ (posedge clk)
	begin
		if (in < 7'd97)
		begin
			out = in;
		end
		else if (in < 8'd194)
		begin
			out = in - 7'd97;
		end
		else if (in < 9'd291)
		begin
			out = in - 8'd194;
		end
		else if (in < 9'd388)
		begin
			out = in - 9'd291;
		end
		else if (in < 9'd485)
		begin
			out = in - 9'd388;
		end
		else
		begin
			out = in - 9'd485;
		end
	end
endmodule



module mult_modulo_97 (koef_pos, in, out, clk);
	input clk;
	input [3:0] koef_pos;
	input [6:0] in;
	output [6:0] out;
	wire [6:0] arr [0:6];

	wire [9:0] interm;

	lut_for_filter_2_pow_0_97 lut0(koef_pos, arr[0]);
	lut_for_filter_2_pow_1_97 lut1(koef_pos, arr[1]);
	lut_for_filter_2_pow_2_97 lut2(koef_pos, arr[2]);
	lut_for_filter_2_pow_3_97 lut3(koef_pos, arr[3]);
	lut_for_filter_2_pow_4_97 lut4(koef_pos, arr[4]);
	lut_for_filter_2_pow_5_97 lut5(koef_pos, arr[5]);
	lut_for_filter_2_pow_6_97 lut6(koef_pos, arr[6]);
	assign interm = arr[0]*in[0] + arr[1]*in[1] + arr[2]*in[2] + arr[3]*in[3] + arr[4]*in[4] + arr[5]*in[5] + arr[6]*in[6];
	mod_97_567_c modul (interm, out, clk);
endmodule

module mod_conv_113 (clk, reset, In, Out, clk_enable);

	input   clk; 
	input   reset; 
	input   clk_enable; 
	input   [6:0] In; 
	output  [6:0] Out; 

    
	wire [6:0] fwd_Out, Mult_out, zerout, inv_Out;
	reg  [3:0] count;
	reg reset2, reset1;

	zero_pad #(7) zero (zerout, In, clk, reset, clk_enable);	
	fft_113 stg1 (clk, clk_enable, reset1, zerout, fwd_Out);
	mult_modulo_113 mlt ({count[0], count[1], count[2], count[3]}, fwd_Out, Mult_out, clk);
	i_fft_113 stg2 (clk, clk_enable, reset2, Mult_out, inv_Out);
	overlap_add_113 add (Out, inv_Out, clk, reset, clk_enable);


	// Sequential blocks that have purpose of !!!MANAGING CLOCKS!!!	
	always @ (posedge clk or posedge reset1)
	begin
		if (reset1)
			count <= 1;
		else 
			count <= count + 1;
	end


	always @ (posedge clk)
	begin
		if (count == 0)	reset2 <= 0;
		if (reset == 0) reset1 <= 0;
		if (reset == 1) begin reset1 <= 1; reset2 <= 1; end
	end
endmodule

module overlap_add_113 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input  clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg clk_2;
	wire [WIDTH-1:0] shift1_out, adder_out;
	
	
	// Block Statements
	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			clk_2 <= 0;
		else 
			clk_2 <= ~clk_2;
	end 


	shift_reg_8 #(WIDTH) shift1 (shift1_out, datain, clk, reset, clk_enable);
	mod_adder #(113, 7) add (adder_out, shift1_out, datain);
	slow_down_8 #(WIDTH) slow (dataout, adder_out, clk, clk_2, reset, clk_enable);

endmodule

module Ind_adder113 (data_out, data_A, data_B);
	parameter p = 113;
	parameter NBRB =7;

	output reg [NBRB-1:0] data_out;
	input [NBRB-1:0] data_A, data_B;
	always @(data_A or data_B)
	begin
		if((data_A == 127) || (data_B == 127) )
			begin
				data_out <= 127;
			end
		else
			begin
				if ({1'b0,data_A} + {1'b0,data_B} < p - 1) data_out <= {1'b0,data_A} + {1'b0,data_B};
				else data_out <= {1'b0,data_A} + {1'b0,data_B} - (p - 1);
			end
	end
endmodule

module Mult_113 (Out, A, gamma);
	parameter WIDTH = 7;
	output	[WIDTH-1:0]	Out;
	input	[WIDTH-1:0]	A, gamma;
	wire [WIDTH-1:0] Index_out, Adder_out;

	Index_ROM_113 #(WIDTH) in1 (Index_out, A);
	Ind_adder113 #(113, WIDTH) add1 (Adder_out, Index_out, gamma);
	Vichet_ROM_113 #(WIDTH) vic1 (Out, Adder_out);

endmodule

module butterfly_113 (A, B, add, sub);
	input   [6:0] A, B; 
	output reg [6:0] add, sub; 


	always @(A or B) 
	begin 
		if ({1'b0, A} + {1'b0, B} < 113) add <= {1'b0, A} + {1'b0, B};
		else add <= {1'b0, A} + {1'b0, B} - (113); 

		if ({1'b0, A} > {1'b0, B}) sub <= {1'b0, B} - {1'b0, A} + (113); 
		else sub <= {1'b0, B} - {1'b0, A}; 
	end 
endmodule

module Index_ROM_113 (data_out, data_x);
	parameter NBRB = 7;
	output reg	[NBRB-1:0]	data_out;
	input 		[NBRB-1:0]	data_x;

	always @(data_x)
	begin
		case(data_x)
		0: data_out <= 127;	
		1: data_out <= 0;	
		2: data_out <= 12;	
		3: data_out <= 1;	
		4: data_out <= 24;	
		5: data_out <= 83;	
		6: data_out <= 13;	
		7: data_out <= 8;	
		8: data_out <= 36;	
		9: data_out <= 2;	
		10: data_out <= 95;	
		11: data_out <= 74;	
		12: data_out <= 25;	
		13: data_out <= 22;	
		14: data_out <= 20;	
		15: data_out <= 84;	
		16: data_out <= 48;	
		17: data_out <= 5;	
		18: data_out <= 14;	
		19: data_out <= 99;	
		20: data_out <= 107;	
		21: data_out <= 9;	
		22: data_out <= 86;	
		23: data_out <= 41;	
		24: data_out <= 37;	
		25: data_out <= 54;	
		26: data_out <= 34;	
		27: data_out <= 3;	
		28: data_out <= 32;	
		29: data_out <= 89;	
		30: data_out <= 96;	
		31: data_out <= 50;	
		32: data_out <= 60;	
		33: data_out <= 75;	
		34: data_out <= 17;	
		35: data_out <= 91;	
		36: data_out <= 26;	
		37: data_out <= 67;	
		38: data_out <= 111;	
		39: data_out <= 23;	
		40: data_out <= 7;	
		41: data_out <= 94;	
		42: data_out <= 21;	
		43: data_out <= 47;	
		44: data_out <= 98;	
		45: data_out <= 85;	
		46: data_out <= 53;	
		47: data_out <= 31;	
		48: data_out <= 49;	
		49: data_out <= 16;	
		50: data_out <= 66;	
		51: data_out <= 6;	
		52: data_out <= 46;	
		53: data_out <= 52;	
		54: data_out <= 15;	
		55: data_out <= 45;	
		56: data_out <= 44;	
		57: data_out <= 100;	
		58: data_out <= 101;	
		59: data_out <= 71;	
		60: data_out <= 108;	
		61: data_out <= 102;	
		62: data_out <= 62;	
		63: data_out <= 10;	
		64: data_out <= 72;	
		65: data_out <= 105;	
		66: data_out <= 87;	
		67: data_out <= 109;	
		68: data_out <= 29;	
		69: data_out <= 42;	
		70: data_out <= 103;	
		71: data_out <= 77;	
		72: data_out <= 38;	
		73: data_out <= 63;	
		74: data_out <= 79;	
		75: data_out <= 55;	
		76: data_out <= 11;	
		77: data_out <= 82;	
		78: data_out <= 35;	
		79: data_out <= 73;	
		80: data_out <= 19;	
		81: data_out <= 4;	
		82: data_out <= 106;	
		83: data_out <= 40;	
		84: data_out <= 33;	
		85: data_out <= 88;	
		86: data_out <= 59;	
		87: data_out <= 90;	
		88: data_out <= 110;	
		89: data_out <= 93;	
		90: data_out <= 97;	
		91: data_out <= 30;	
		92: data_out <= 65;	
		93: data_out <= 51;	
		94: data_out <= 43;	
		95: data_out <= 70;	
		96: data_out <= 61;	
		97: data_out <= 104;	
		98: data_out <= 28;	
		99: data_out <= 76;	
		100: data_out <= 78;	
		101: data_out <= 81;	
		102: data_out <= 18;	
		103: data_out <= 39;	
		104: data_out <= 58;	
		105: data_out <= 92;	
		106: data_out <= 64;	
		107: data_out <= 69;	
		108: data_out <= 27;	
		109: data_out <= 80;	
		110: data_out <= 57;	
		111: data_out <= 68;	
		112: data_out <= 56;	
		default data_out <= 127;
		endcase
	end
endmodule

module Vichet_ROM_113 (data_out, data_x);
	parameter NBRB = 7;
	output reg	[NBRB-1:0]	data_out;
	input 		[NBRB-1:0]	data_x;

	always @(data_x)
	begin	
		case(data_x)
			0: data_out <= 1;	
		1: data_out <= 3;	
		2: data_out <= 9;	
		3: data_out <= 27;	
		4: data_out <= 81;	
		5: data_out <= 17;	
		6: data_out <= 51;	
		7: data_out <= 40;	
		8: data_out <= 7;	
		9: data_out <= 21;	
		10: data_out <= 63;	
		11: data_out <= 76;	
		12: data_out <= 2;	
		13: data_out <= 6;	
		14: data_out <= 18;	
		15: data_out <= 54;	
		16: data_out <= 49;	
		17: data_out <= 34;	
		18: data_out <= 102;	
		19: data_out <= 80;	
		20: data_out <= 14;	
		21: data_out <= 42;	
		22: data_out <= 13;	
		23: data_out <= 39;	
		24: data_out <= 4;	
		25: data_out <= 12;	
		26: data_out <= 36;	
		27: data_out <= 108;	
		28: data_out <= 98;	
		29: data_out <= 68;	
		30: data_out <= 91;	
		31: data_out <= 47;	
		32: data_out <= 28;	
		33: data_out <= 84;	
		34: data_out <= 26;	
		35: data_out <= 78;	
		36: data_out <= 8;	
		37: data_out <= 24;	
		38: data_out <= 72;	
		39: data_out <= 103;	
		40: data_out <= 83;	
		41: data_out <= 23;	
		42: data_out <= 69;	
		43: data_out <= 94;	
		44: data_out <= 56;	
		45: data_out <= 55;	
		46: data_out <= 52;	
		47: data_out <= 43;	
		48: data_out <= 16;	
		49: data_out <= 48;	
		50: data_out <= 31;	
		51: data_out <= 93;	
		52: data_out <= 53;	
		53: data_out <= 46;	
		54: data_out <= 25;	
		55: data_out <= 75;	
		56: data_out <= 112;	
		57: data_out <= 110;	
		58: data_out <= 104;	
		59: data_out <= 86;	
		60: data_out <= 32;	
		61: data_out <= 96;	
		62: data_out <= 62;	
		63: data_out <= 73;	
		64: data_out <= 106;	
		65: data_out <= 92;	
		66: data_out <= 50;	
		67: data_out <= 37;	
		68: data_out <= 111;	
		69: data_out <= 107;	
		70: data_out <= 95;	
		71: data_out <= 59;	
		72: data_out <= 64;	
		73: data_out <= 79;	
		74: data_out <= 11;	
		75: data_out <= 33;	
		76: data_out <= 99;	
		77: data_out <= 71;	
		78: data_out <= 100;	
		79: data_out <= 74;	
		80: data_out <= 109;	
		81: data_out <= 101;	
		82: data_out <= 77;	
		83: data_out <= 5;	
		84: data_out <= 15;	
		85: data_out <= 45;	
		86: data_out <= 22;	
		87: data_out <= 66;	
		88: data_out <= 85;	
		89: data_out <= 29;	
		90: data_out <= 87;	
		91: data_out <= 35;	
		92: data_out <= 105;	
		93: data_out <= 89;	
		94: data_out <= 41;	
		95: data_out <= 10;	
		96: data_out <= 30;	
		97: data_out <= 90;	
		98: data_out <= 44;	
		99: data_out <= 19;	
		100: data_out <= 57;	
		101: data_out <= 58;	
		102: data_out <= 61;	
		103: data_out <= 70;	
		104: data_out <= 97;	
		105: data_out <= 65;	
		106: data_out <= 82;	
		107: data_out <= 20;	
		108: data_out <= 60;	
		109: data_out <= 67;	
		110: data_out <= 88;	
		111: data_out <= 38;	
		default data_out <= 0;
		endcase
	end
endmodule

module manager_113 (stg1_out, stg2_out, stg3_out, in_count, clk);
	parameter WIDTH=7; 
	input                  clk;
	input [3:0]            in_count;	
	output reg [WIDTH-1:0] stg1_out, stg2_out, stg3_out; 
 
 
	always @ (posedge clk)
	begin
	//koeff on 1-st stage 
	case(in_count[3:0]) 	
	    15: begin 
	    stg1_out<= 0; 
		end
	    0: begin 
	    stg1_out<= 7; 
		end
	    1: begin 
	    stg1_out<= 14; 
		end
	    2: begin 
	    stg1_out<= 21; 
		end
	    3: begin 
	    stg1_out<= 28; 
		end
	    4: begin 
	    stg1_out<= 35; 
		end
	    5: begin 
	    stg1_out<= 42; 
		end
	    6: begin 
	    stg1_out<= 49; 
		end
	    7: begin 
	    stg1_out<= 0; 
		end
	    8: begin 
	    stg1_out<= 0; 
		end
	    9: begin 
	    stg1_out<= 0; 
		end
	    10: begin 
	    stg1_out<= 0; 
		end
	    11: begin 
	    stg1_out<= 0; 
		end
	    12: begin 
	    stg1_out<= 0; 
		end
	    13: begin 
	    stg1_out<= 0; 
		end
	    14: begin 
	    stg1_out<= 0; 
		end
	endcase
	//koeff on 2-st stage 
	case(in_count[2:0]) 	
	    7: begin 
	    stg2_out<= 0; 
		end
	    0: begin 
	    stg2_out<= 14; 
		end
	    1: begin 
	    stg2_out<= 28; 
		end
	    2: begin 
	    stg2_out<= 42; 
		end
	    3: begin 
	    stg2_out<= 0; 
		end
	    4: begin 
	    stg2_out<= 0; 
		end
	    5: begin 
	    stg2_out<= 0; 
		end
	    6: begin 
	    stg2_out<= 0; 
		end
	endcase
	//koeff on 3-st stage 
	case(in_count[1:0]) 	
	    3: begin 
	    stg3_out<= 0; 
		end
	    0: begin 
	    stg3_out<= 28; 
		end
	    1: begin 
	    stg3_out<= 0; 
		end
	    2: begin 
	    stg3_out<= 0; 
		end
	endcase

	end

endmodule

module stage_113_8 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mux_Out;


	butterfly_113 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (mux_Out, butt_add, shiftout, sel); 
	shift_reg_8 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_113 mult (Out, mux_Out, gamma);     
	//assign Out = mux_Out; 

endmodule

module stage_113_4 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mux_Out;


	butterfly_113 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (mux_Out, butt_add, shiftout, sel); 
	shift_reg_4 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_113 mult (Out, mux_Out, gamma);     
	//assign Out = mux_Out; 

endmodule

module stage_113_2 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mux_Out;


	butterfly_113 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (mux_Out, butt_add, shiftout, sel); 
	shift_reg_2 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_113 mult (Out, mux_Out, gamma);     
	//assign Out = mux_Out; 

endmodule

module stage_113_1 (clk, clk_enable, reset, In, Out, sel);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub;


	butterfly_113 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_1 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);


endmodule

module fft_113 (clk, clk_enable, reset, In, Out);

	input   clk; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 
	reg [3:0] count;

	wire [6:0] Stg1_out, Stg2_out, Stg3_out;
	wire [6:0] stg1_coeff, stg2_coeff, stg3_coeff;

	stage_113_8 stg1 (clk, clk_enable, reset, In, Stg1_out, count[3], stg1_coeff);
	stage_113_4 stg2 (clk, clk_enable, reset, Stg1_out, Stg2_out, count[2], stg2_coeff);
	stage_113_2 stg3 (clk, clk_enable, reset, Stg2_out, Stg3_out, count[1], stg3_coeff);
	stage_113_1 stg4 (clk, clk_enable, reset, Stg3_out, Out, count[0]);
	manager_113 mng  (stg1_coeff, stg2_coeff, stg3_coeff, count, clk);	


	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			count <= 0;
		else if (clk_enable == 1'b1)
			count <= count + 1;
	end
endmodule

module i_manager_113 (stg1_out, stg2_out, stg3_out, in_count, clk);
	parameter WIDTH=7; 
	input                  clk;
	input [3:0]            in_count;	
	output reg [WIDTH-1:0] stg1_out, stg2_out, stg3_out; 
 
 
	always @ (posedge clk) 
	begin  
	//koeff on 1-st stage 
	case(in_count[3:0]) 	
	    0: begin 
	    stg1_out<= 64; 
		end
	    15: begin 
	    stg1_out<= 57; 
		end
	    14: begin 
	    stg1_out<= 50; 
		end
	    13: begin 
	    stg1_out<= 43; 
		end
	    12: begin 
	    stg1_out<= 36; 
		end
	    11: begin 
	    stg1_out<= 29; 
		end
	    10: begin 
	    stg1_out<= 22; 
		end
	    9: begin 
	    stg1_out<= 15; 
		end
	    8: begin 
	    stg1_out<= 64; 
		end
	    7: begin 
	    stg1_out<= 64; 
		end
	    6: begin 
	    stg1_out<= 64; 
		end
	    5: begin 
	    stg1_out<= 64; 
		end
	    4: begin 
	    stg1_out<= 64; 
		end
	    3: begin 
	    stg1_out<= 64; 
		end
	    2: begin 
	    stg1_out<= 64; 
		end
	    1: begin 
	    stg1_out<= 64; 
		end
	endcase 

	//koeff on 2-st stage
	case(in_count[2:0])
	    0: begin 
	    stg2_out<= 0; 
		end
	    7: begin 
	    stg2_out<= 98; 
		end
	    6: begin 
	    stg2_out<= 84; 
		end
	    5: begin 
	    stg2_out<= 70; 
		end
	    4: begin 
	    stg2_out<= 0; 
		end
	    3: begin 
	    stg2_out<= 0; 
		end
	    2: begin 
	    stg2_out<= 0; 
		end
	    1: begin 
	    stg2_out<= 0; 
		end
	endcase

	//koeff on 3-st stage
	case(in_count[1:0])
	    0: begin 
	    stg3_out<= 0; 
		end
	    3: begin 
	    stg3_out<= 84; 
		end
	    2: begin 
	    stg3_out<= 0; 
		end
	    1: begin 
	    stg3_out<= 0; 
		end
	endcase

	end

endmodule

module i_stage_113_8 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mult_Out;


	butterfly_113 butt (mult_Out, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, mult_Out, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_8 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_113 mult (mult_Out, In, gamma);     
	//assign Out = mux_Out; 

endmodule

module i_stage_113_4 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mult_Out;


	butterfly_113 butt (mult_Out, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_4 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_113 mult (mult_Out, In, gamma);     
	//assign Out = mux_Out; 

endmodule

module i_stage_113_2 (clk, clk_enable, reset, In, Out, sel, gamma);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In, gamma; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub, mult_Out;


	butterfly_113 butt (mult_Out, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_2 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);
	Mult_113 mult (mult_Out, In, gamma);     
	//assign Out = mux_Out; 

endmodule

module i_stage_113_1 (clk, clk_enable, reset, In, Out, sel);

	input   clk, sel; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 

	wire [6:0] shiftout, shiftin, butt_add, butt_sub;


	butterfly_113 butt (In, shiftout, butt_add, butt_sub);
	mux #(.WIDTH(7)) m1 (shiftin, butt_sub, In, sel);
	mux #(.WIDTH(7)) m2 (Out, butt_add, shiftout, sel); 
	shift_reg_1 #(.WIDTH(7)) shr (shiftout, shiftin, clk, reset, clk_enable);


endmodule

module i_fft_113 (clk, clk_enable, reset, In, Out);

	input   clk; 
	input   clk_enable; 
	input   reset; 
	input   [6:0] In; 
	output  [6:0] Out; 
	reg [3:0] count;

	wire [6:0] Stg1_out, Stg2_out, Stg3_out;
	wire [6:0] stg1_coeff, stg2_coeff, stg3_coeff;

	i_stage_113_1 stg1 (clk, clk_enable, reset, In, Stg1_out, count[0]);
	i_stage_113_2 stg2 (clk, clk_enable, reset, Stg1_out, Stg2_out, count[1], stg3_coeff);
	i_stage_113_4 stg3 (clk, clk_enable, reset, Stg2_out, Stg3_out, count[2], stg2_coeff);
	i_stage_113_8 stg4 (clk, clk_enable, reset, Stg3_out, Out, count[3], stg1_coeff);
	i_manager_113 mng  (stg1_coeff, stg2_coeff, stg3_coeff, count, clk);	


	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			count <= 14;
		else if (clk_enable == 1'b1)
			count <= count - 1;
	end
endmodule



module lut_for_filter_2_pow_0_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 48;
		1: out = 98;
		2: out = 101;
		3: out = 87;
		4: out = 71;
		5: out = 38;
		6: out = 78;
		7: out = 11;
		8: out = 69;
		9: out = 65;
		10: out = 58;
		11: out = 65;
		12: out = 95;
		13: out = 95;
		14: out = 28;
		15: out = 89;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_1_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 96;
		1: out = 83;
		2: out = 89;
		3: out = 61;
		4: out = 29;
		5: out = 76;
		6: out = 43;
		7: out = 22;
		8: out = 25;
		9: out = 17;
		10: out = 3;
		11: out = 17;
		12: out = 77;
		13: out = 77;
		14: out = 56;
		15: out = 65;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_2_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 79;
		1: out = 53;
		2: out = 65;
		3: out = 9;
		4: out = 58;
		5: out = 39;
		6: out = 86;
		7: out = 44;
		8: out = 50;
		9: out = 34;
		10: out = 6;
		11: out = 34;
		12: out = 41;
		13: out = 41;
		14: out = 112;
		15: out = 17;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_3_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 45;
		1: out = 106;
		2: out = 17;
		3: out = 18;
		4: out = 3;
		5: out = 78;
		6: out = 59;
		7: out = 88;
		8: out = 100;
		9: out = 68;
		10: out = 12;
		11: out = 68;
		12: out = 82;
		13: out = 82;
		14: out = 111;
		15: out = 34;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_4_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 90;
		1: out = 99;
		2: out = 34;
		3: out = 36;
		4: out = 6;
		5: out = 43;
		6: out = 5;
		7: out = 63;
		8: out = 87;
		9: out = 23;
		10: out = 24;
		11: out = 23;
		12: out = 51;
		13: out = 51;
		14: out = 109;
		15: out = 68;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_5_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 67;
		1: out = 85;
		2: out = 68;
		3: out = 72;
		4: out = 12;
		5: out = 86;
		6: out = 10;
		7: out = 13;
		8: out = 61;
		9: out = 46;
		10: out = 48;
		11: out = 46;
		12: out = 102;
		13: out = 102;
		14: out = 105;
		15: out = 23;
		default: out = 0; 
	endcase 
endmodule


module lut_for_filter_2_pow_6_113 (koef_pos, out);
	input [3:0] koef_pos;
	output reg [6:0] out;
	always @ (koef_pos)
	case(koef_pos) 
		0: out = 21;
		1: out = 57;
		2: out = 23;
		3: out = 31;
		4: out = 24;
		5: out = 59;
		6: out = 20;
		7: out = 26;
		8: out = 9;
		9: out = 92;
		10: out = 96;
		11: out = 92;
		12: out = 91;
		13: out = 91;
		14: out = 97;
		15: out = 46;
		default: out = 0; 
	endcase 
endmodule

module mod_113_618_c (in, out, clk);
	input clk;
	input [9:0] in;
	output reg [6:0] out;
	always @ (posedge clk)
	begin
		if (in < 7'd113)
		begin
			out = in;
		end
		else if (in < 8'd226)
		begin
			out = in - 7'd113;
		end
		else if (in < 9'd339)
		begin
			out = in - 8'd226;
		end
		else if (in < 9'd452)
		begin
			out = in - 9'd339;
		end
		else if (in < 10'd565)
		begin
			out = in - 9'd452;
		end
		else
		begin
			out = in - 10'd565;
		end
	end
endmodule



module mult_modulo_113 (koef_pos, in, out, clk);
	input clk;
	input [3:0] koef_pos;
	input [6:0] in;
	output [6:0] out;
	wire [6:0] arr [0:6];

	wire [9:0] interm;

	lut_for_filter_2_pow_0_113 lut0(koef_pos, arr[0]);
	lut_for_filter_2_pow_1_113 lut1(koef_pos, arr[1]);
	lut_for_filter_2_pow_2_113 lut2(koef_pos, arr[2]);
	lut_for_filter_2_pow_3_113 lut3(koef_pos, arr[3]);
	lut_for_filter_2_pow_4_113 lut4(koef_pos, arr[4]);
	lut_for_filter_2_pow_5_113 lut5(koef_pos, arr[5]);
	lut_for_filter_2_pow_6_113 lut6(koef_pos, arr[6]);
	assign interm = arr[0]*in[0] + arr[1]*in[1] + arr[2]*in[2] + arr[3]*in[3] + arr[4]*in[4] + arr[5]*in[5] + arr[6]*in[6];
	mod_113_618_c modul (interm, out, clk);
endmodule

module shift_reg_8 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;

	reg  [WIDTH-1:0] delay_pipeline [0:7] ;


	// Block Statements
	always @( posedge clk or posedge reset)
		begin: Delay_Pipeline_process
		if (reset == 1'b1) begin
			delay_pipeline[0] <= 0;
			delay_pipeline[1] <= 0;
			delay_pipeline[2] <= 0;
			delay_pipeline[3] <= 0;
			delay_pipeline[4] <= 0;
			delay_pipeline[5] <= 0;
			delay_pipeline[6] <= 0;
			delay_pipeline[7] <= 0;
		end
		else begin
			if (clk_enable == 1'b1) begin
				delay_pipeline[0] <= datain;
				delay_pipeline[1] <= delay_pipeline[0];
				delay_pipeline[2] <= delay_pipeline[1];
				delay_pipeline[3] <= delay_pipeline[2];
				delay_pipeline[4] <= delay_pipeline[3];
				delay_pipeline[5] <= delay_pipeline[4];
				delay_pipeline[6] <= delay_pipeline[5];
				delay_pipeline[7] <= delay_pipeline[6];
			end
		end
	end // Delay_Pipeline_process
	assign dataout = delay_pipeline[7]; // connection to dataout

endmodule

module shift_reg_4 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;

	reg  [WIDTH-1:0] delay_pipeline [0:3] ;


	// Block Statements
	always @( posedge clk or posedge reset)
		begin: Delay_Pipeline_process
		if (reset == 1'b1) begin
			delay_pipeline[0] <= 0;
			delay_pipeline[1] <= 0;
			delay_pipeline[2] <= 0;
			delay_pipeline[3] <= 0;
		end
		else begin
			if (clk_enable == 1'b1) begin
				delay_pipeline[0] <= datain;
				delay_pipeline[1] <= delay_pipeline[0];
				delay_pipeline[2] <= delay_pipeline[1];
				delay_pipeline[3] <= delay_pipeline[2];
			end
		end
	end // Delay_Pipeline_process
	assign dataout = delay_pipeline[3]; // connection to dataout

endmodule

module shift_reg_2 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;

	reg  [WIDTH-1:0] delay_pipeline [0:1] ;


	// Block Statements
	always @( posedge clk or posedge reset)
		begin: Delay_Pipeline_process
		if (reset == 1'b1) begin
			delay_pipeline[0] <= 0;
			delay_pipeline[1] <= 0;
		end
		else begin
			if (clk_enable == 1'b1) begin
				delay_pipeline[0] <= datain;
				delay_pipeline[1] <= delay_pipeline[0];
			end
		end
	end // Delay_Pipeline_process
	assign dataout = delay_pipeline[1]; // connection to dataout

endmodule

module shift_reg_1 (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;

	reg  [WIDTH-1:0] delay_pipeline [0:0] ;


	// Block Statements
	always @( posedge clk or posedge reset)
		begin: Delay_Pipeline_process
		if (reset == 1'b1) begin
			delay_pipeline[0] <= 0;
		end
		else begin
			if (clk_enable == 1'b1) begin
				delay_pipeline[0] <= datain;
			end
		end
	end // Delay_Pipeline_process
	assign dataout = delay_pipeline[0]; // connection to dataout

endmodule

module mux (res, dataa, datab, sel);
	parameter WIDTH=7;

	input   [WIDTH-1:0] dataa;
	input   [WIDTH-1:0] datab;
	input                 sel;
	output reg  [WIDTH-1:0]   res;
	
always @ (sel or dataa or datab)
	begin
	case(sel)
	1'b0: res = datab;
	1'b1: res = dataa;
	endcase
end
endmodule
module zero_pad (dataout, datain, clk, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input              clk, reset, clk_enable;
	output [WIDTH-1:0] dataout;
	
	reg  [WIDTH-1:0] delay_pipeline_1 [0:15];
	reg  [WIDTH-1:0] delay_pipeline_2 [0:15];
	reg  [3:0] count;

  // Block Statements
 	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			count <= 1;
		else 
			count <= count + 1;
	end 
 
  
  always @( posedge clk or posedge reset)
    begin: Delay_Pipeline_process
      if (reset == 1'b1) 
		begin
        delay_pipeline_1[0] <= 0;
        delay_pipeline_1[1] <= 0;
        delay_pipeline_1[2] <= 0;
        delay_pipeline_1[3] <= 0;
        delay_pipeline_1[4] <= 0;
        delay_pipeline_1[5] <= 0;
        delay_pipeline_1[6] <= 0;
        delay_pipeline_1[7] <= 0;
        delay_pipeline_1[8] <= 0;
        delay_pipeline_1[9] <= 0;
        delay_pipeline_1[10] <= 0;
        delay_pipeline_1[11] <= 0;
        delay_pipeline_1[12] <= 0;
        delay_pipeline_1[13] <= 0;
        delay_pipeline_1[14] <= 0;
        delay_pipeline_1[15] <= 0;
        delay_pipeline_2[0] <= 0;
        delay_pipeline_2[1] <= 0;
        delay_pipeline_2[2] <= 0;
        delay_pipeline_2[3] <= 0;
        delay_pipeline_2[4] <= 0;
        delay_pipeline_2[5] <= 0;
        delay_pipeline_2[6] <= 0;
        delay_pipeline_2[7] <= 0;
        delay_pipeline_2[8] <= 0;
        delay_pipeline_2[9] <= 0;
        delay_pipeline_2[10] <= 0;
        delay_pipeline_2[11] <= 0;
        delay_pipeline_2[12] <= 0;
        delay_pipeline_2[13] <= 0;
        delay_pipeline_2[14] <= 0;
        delay_pipeline_2[15] <= 0;
        end
      else 
	  begin
		if (count == 0) 
			begin
   			delay_pipeline_2[0] <= delay_pipeline_1[0];
   			delay_pipeline_2[1] <= delay_pipeline_1[2];
   			delay_pipeline_2[2] <= delay_pipeline_1[4];
   			delay_pipeline_2[3] <= delay_pipeline_1[6];
   			delay_pipeline_2[4] <= delay_pipeline_1[8];
   			delay_pipeline_2[5] <= delay_pipeline_1[10];
   			delay_pipeline_2[6] <= delay_pipeline_1[12];
   			delay_pipeline_2[7] <= delay_pipeline_1[14];
   			delay_pipeline_2[8] <= 0;
   			delay_pipeline_2[9] <= 0;
   			delay_pipeline_2[10] <= 0;
   			delay_pipeline_2[11] <= 0;
   			delay_pipeline_2[12] <= 0;
   			delay_pipeline_2[13] <= 0;
   			delay_pipeline_2[14] <= 0;
   			delay_pipeline_2[15] <= 0;
			end
		else
		begin
	  		if (clk_enable == 1'b1) 
				begin		
				delay_pipeline_1[0] <= datain;		
				delay_pipeline_1[1] <= delay_pipeline_1[0];
				delay_pipeline_1[2] <= delay_pipeline_1[1];
				delay_pipeline_1[3] <= delay_pipeline_1[2];
				delay_pipeline_1[4] <= delay_pipeline_1[3];
				delay_pipeline_1[5] <= delay_pipeline_1[4];
				delay_pipeline_1[6] <= delay_pipeline_1[5];
				delay_pipeline_1[7] <= delay_pipeline_1[6];
				delay_pipeline_1[8] <= delay_pipeline_1[7];
				delay_pipeline_1[9] <= delay_pipeline_1[8];
				delay_pipeline_1[10] <= delay_pipeline_1[9];
				delay_pipeline_1[11] <= delay_pipeline_1[10];
				delay_pipeline_1[12] <= delay_pipeline_1[11];
				delay_pipeline_1[13] <= delay_pipeline_1[12];
				delay_pipeline_1[14] <= delay_pipeline_1[13];
				delay_pipeline_1[15] <= delay_pipeline_1[14];
				delay_pipeline_2[1] <= delay_pipeline_2[0];
				delay_pipeline_2[2] <= delay_pipeline_2[1];
				delay_pipeline_2[3] <= delay_pipeline_2[2];
				delay_pipeline_2[4] <= delay_pipeline_2[3];
				delay_pipeline_2[5] <= delay_pipeline_2[4];
				delay_pipeline_2[6] <= delay_pipeline_2[5];
				delay_pipeline_2[7] <= delay_pipeline_2[6];
				delay_pipeline_2[8] <= delay_pipeline_2[7];
				delay_pipeline_2[9] <= delay_pipeline_2[8];
				delay_pipeline_2[10] <= delay_pipeline_2[9];
				delay_pipeline_2[11] <= delay_pipeline_2[10];
				delay_pipeline_2[12] <= delay_pipeline_2[11];
				delay_pipeline_2[13] <= delay_pipeline_2[12];
				delay_pipeline_2[14] <= delay_pipeline_2[13];
				delay_pipeline_2[15] <= delay_pipeline_2[14];
				end
        end
      end
    end // Delay_Pipeline_process
assign dataout = delay_pipeline_2[15]; // connection to dataout
endmodule		
module impulse (clk, in, out);
	input  			   in;
	input              clk;
	output 			   out;
	reg temp;
	
	always @ (posedge clk)
	begin
		if (in == 1)
		begin
			temp <= 1;
		end
		else temp <= 0;
	end 
	assign out = (~temp)&in;
endmodule
module slow_down_8 (dataout, datain, clk, clk_2, reset, clk_enable);
	parameter WIDTH=7;	
	input  [WIDTH-1:0] datain;
	input              clk, clk_2, reset, clk_enable;
	output [WIDTH-1:0] dataout;

	reg  [WIDTH-1:0] delay_pipeline [0:7];
	reg  [WIDTH-1:0] delay_pipeline2 [0:8];
	reg  [3:0] count;
	wire trigger;
	// Block Statements
	impulse trig (clk, count[3], trigger);


	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			count <= 0;
		else 
			count <= count + 1;
	end 	

	always @( posedge clk or posedge reset)
	begin: Delay_Pipeline_process1
      if (reset == 1'b1) begin
        delay_pipeline[0] <= 0;
        delay_pipeline[1] <= 0;
        delay_pipeline[2] <= 0;
        delay_pipeline[3] <= 0;
        delay_pipeline[4] <= 0;
        delay_pipeline[5] <= 0;
        delay_pipeline[6] <= 0;
        delay_pipeline[7] <= 0;
        end
      else begin
        if (clk_enable == 1'b1) begin
          delay_pipeline[0] <= datain;
        delay_pipeline[1] <= delay_pipeline[0];
        delay_pipeline[2] <= delay_pipeline[1];
        delay_pipeline[3] <= delay_pipeline[2];
        delay_pipeline[4] <= delay_pipeline[3];
        delay_pipeline[5] <= delay_pipeline[4];
        delay_pipeline[6] <= delay_pipeline[5];
        delay_pipeline[7] <= delay_pipeline[6];
        end
      end
 end // Delay_Pipeline_process

	always @( posedge clk_2 or posedge reset or posedge trigger)
 begin: Delay_Pipeline_process2
      if (reset == 1'b1) begin
        delay_pipeline2[0] <= 0;
        delay_pipeline2[1] <= 0;
        delay_pipeline2[2] <= 0;
        delay_pipeline2[3] <= 0;
        delay_pipeline2[4] <= 0;
        delay_pipeline2[5] <= 0;
        delay_pipeline2[6] <= 0;
        delay_pipeline2[7] <= 0;
        delay_pipeline2[8] <= 0;
        end
      else begin
		if (trigger) begin
        delay_pipeline2[0] <= delay_pipeline[0];
        delay_pipeline2[1] <= delay_pipeline[1];
        delay_pipeline2[2] <= delay_pipeline[2];
        delay_pipeline2[3] <= delay_pipeline[3];
        delay_pipeline2[4] <= delay_pipeline[4];
        delay_pipeline2[5] <= delay_pipeline[5];
        delay_pipeline2[6] <= delay_pipeline[6];
        delay_pipeline2[7] <= delay_pipeline[7];
     end 
      else begin
        if (clk_enable == 1'b1) begin
        delay_pipeline2[1] <= delay_pipeline2[0];
        delay_pipeline2[2] <= delay_pipeline2[1];
        delay_pipeline2[3] <= delay_pipeline2[2];
        delay_pipeline2[4] <= delay_pipeline2[3];
        delay_pipeline2[5] <= delay_pipeline2[4];
        delay_pipeline2[6] <= delay_pipeline2[5];
        delay_pipeline2[7] <= delay_pipeline2[6];
        delay_pipeline2[8] <= delay_pipeline2[7];
        end
        end
      end
    end // Delay_Pipeline_process		


	assign dataout = delay_pipeline2[8]; // connection to dataout
endmodule

module mod_adder (data_out, data_A, data_B);
	parameter p = 97;
	parameter NBRB =7;

	output reg		[NBRB-1:0]	data_out;
	input  			[NBRB-1:0]	data_A, data_B;
	always @(data_A or data_B)
	begin
				if ({1'b0,data_A} + {1'b0,data_B} < p) data_out <= {1'b0,data_A} + {1'b0,data_B};
				else data_out <= {1'b0,data_A} + {1'b0,data_B} - (p);
	end
endmodule

module lut_97_113(out, a, b, clk);
	input [6:0] a;
	input [6:0] b;
	reg [6:0] inter;
	wire [8:0] bmod;
	input clk;
	output wire [6:0] out;

	assign bmod = 7*inter[0] + 14*inter[1] + 28*inter[2] + 56*inter[3] + 112*inter[4] + 111*inter[5] + 109*inter[6];
	mod_113_437_nc mod (bmod, out);
	
	always @ (posedge clk) 
	begin 

		if (b >= a)
		begin 
			inter = b - a;
		end 
		else 
		begin 
			inter = 113 + b - a;
		end 
	end
endmodule

module mod_113_437_nc (in, out);
	input [8:0] in;
	output reg [6:0] out;
	always @ (in)
	begin
		if (in < 7'd113)
		begin
			out = in;
		end
		else if (in < 8'd226)
		begin
			out = in - 7'd113;
		end
		else if (in < 9'd339)
		begin
			out = in - 8'd226;
		end
		else
		begin
			out = in - 9'd339;
		end
	end
endmodule

module mult113(out, data);

	input [6:0] data;
	output reg [13:0] out;
	
	always @ (data) 
	begin
		out <= 97*data;
	end
endmodule

module register(res, x, clk);
	parameter WIDTH=3;
	input  clk;
	input  [WIDTH-1:0] x;
	output reg [WIDTH-1:0] res;

	always @ (posedge clk)
	begin
		res <= x;
	end
endmodule

module adder(result, dataa, datab, clk);
	parameter WIDTH_A=3;
	parameter WIDTH_B=8;
	parameter WIDTH_C=8;
	input clk;
	input  [WIDTH_A - 1:0] dataa;
	input  [WIDTH_B - 1:0] datab;
	output reg [WIDTH_C:0] result;

	always @ (posedge clk) 
	begin 
		result <= dataa + datab;
	end
endmodule

module mix_rdx (res1, res2, x1, x2, clk); 

	input clk;
	input	[6:0] x1;
	input	[6:0] x2;

	output	[6:0] res1;
	output	[6:0] res2;
	

	assign res1 = x1;

	lut_97_113 l97_113 (res2, x1, x2, clk);
endmodule

module par_adder(result, x1, x2, clk);

	input clk;
	input [6:0] x1;
	input [13:0] x2;
	output [13:0] result;
	wire [6:0] reg1out;

	register #(.WIDTH(7)) reg1 (reg1out, x1, clk);
	adder #(.WIDTH_A(7), .WIDTH_B(14), .WIDTH_C(13)) add1 (result, reg1out, x2, clk);
endmodule

module reverse_conv(result, x1, x2, clk);

	input clk;
	input [6:0] x1;
	input [6:0] x2;
	output [13:0] result;

	wire [6:0] mix_rdx1out;
	wire [6:0] mix_rdx2out;

	wire [13:0] mult113out;
	mix_rdx mix1 (mix_rdx1out, mix_rdx2out, x1, x2, clk);
	mult113 m113 (mult113out, mix_rdx2out);
	par_adder pa (result, mix_rdx1out, mult113out, clk);

endmodule

module forward_conv (out0, out1, in);
	output [6:0] out0; // Module: 97
	output [6:0] out1; // Module: 113
	input [2:0] in; // Max value: 7

	forward_conv_module_97 inst97(in, out0);
	forward_conv_module_113 inst113(in, out1);
endmodule

module forward_conv_module_97 (in, out);
	input [2:0] in; // Max value: 7
	output [6:0] out; // Max value: 96
	assign out = {1'd0,1'd0,1'd0,1'd0,in[2:0]};
endmodule

module forward_conv_module_113 (in, out);
	input [2:0] in; // Max value: 7
	output [6:0] out; // Max value: 112
	assign out = {1'd0,1'd0,1'd0,1'd0,in[2:0]};
endmodule

module fir_filter (in, out, clk, reset, clk_enable);
	input [2:0] in;
	input clk;
	input reset;
	input clk_enable;
	output [13:0] out;
	
	
	wire  [6:0] fwd_out_97, conv_out_97; // Module: 97
	wire  [6:0] fwd_out_113, conv_out_113; // Module: 113
	
	forward_conv fwd (fwd_out_97, fwd_out_113, in);
	mod_conv_97 conv97 (clk, reset, fwd_out_97, conv_out_97, clk_enable);
	mod_conv_113 conv113 (clk, reset, fwd_out_113, conv_out_113, clk_enable);
	reverse_conv rws (out, conv_out_97, conv_out_113, clk);	
endmodule
Описание:
1. Испольуется подход описанный здесь: Разработка модулярного КИХ фильтра на базе теоретико-числового БПФ