Model { Name "modul_convolution" Version 7.9 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.277" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "UTF-8" slprops.hdlmdlprops { $PropName "HDLParams" $ObjectID 1 Array { Type "Cell" Dimension 14 Cell "Backannotation" Cell "on" Cell "FamilyDevicePackageSpeed" Array { Type "Cell" Dimension 4 Cell "Cyclone IV E" Cell "EP4CE115F29C9L" Cell "" Cell "" PropName "Cell" } Cell "HDLSubsystem" Cell "modul_convolution/FIR_complex" Cell "MaskParameterAsGeneric" Cell "on" Cell "MinimizeIntermediateSignals" Cell "on" Cell "TargetDirectory" Cell "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/hdl_convolution_complex/hdlsrc" Cell "TargetLanguage" Cell "Verilog" PropName "mdlProps" } } SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" FPTRunName "Run 1" MaxMDLFileLineLength 120 InitFcn "%% DSPBuilder Start\nalt_dspbuilder_update_model(bdroot)\n%% DSPBuilder End\n" Created "Thu Jun 05 10:45:34 2014" Creator "root" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "root" ModifiedDateFormat "%" LastModifiedDate "Fri Sep 26 12:15:59 2014" RTWModifiedTimeStamp 333546380 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "disabled" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowDesignRanges off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off Object { $PropName "DataLoggingOverride" $ObjectID 2 $ClassName "Simulink.SimulationData.ModelLoggingInfo" model_ "modul_convolution" overrideMode_ [0.0] Array { Type "Cell" Dimension 1 Cell "modul_convolution" PropName "logAsSpecifiedByModels_" } Array { Type "Cell" Dimension 1 Cell [] PropName "logAsSpecifiedByModelsSSIDs_" } } RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 3 Version "1.12.0" Array { Type "Handle" Dimension 9 Simulink.SolverCC { $ObjectID 4 Version "1.12.0" StartTime "0.0" StopTime "500" AbsTol "auto" FixedStep "1" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "Auto" EnableConcurrentExecution off ConcurrentTasks off Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 5 Version "1.12.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 6 Version "1.12.0" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction off BooleanDataType on ConditionallyExecuteInputs off InlineParams off UseIntDivNetSlope off UseFloatMulNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off ParallelExecutionInRapidAccelerator on } Simulink.DebuggingCC { $ObjectID 7 Version "1.12.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Enable All" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" FrameProcessingCompatibilityMsg "warning" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" } Simulink.HardwareCC { $ObjectID 8 Version "1.12.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 9 Version "1.12.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 10 Version "1.12.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 11 Version "1.12.0" Array { Type "Cell" Dimension 9 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateWebview" Cell "GenerateCodeMetricsReport" Cell "GenerateCodeReplacementReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateWebview off GenerateCodeMetricsReport off GenerateCodeReplacementReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 12 Version "1.12.0" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 13 Version "1.12.0" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" CodeReplacementLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on ConcurrentExecutionCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns on CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off GRTInterface off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } hdlcoderui.hdlcc { $ObjectID 14 Version "1.12.0" Description "HDL Coder custom configuration component" Name "HDL Coder" Array { Type "Cell" Dimension 1 Cell "" PropName "HDLConfigFile" } HDLCActiveTab "0" } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 208, 77, 1097, 652 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 3 } ExplicitPartitioning off BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType DataTypeConversion OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit via back propagation" LockScale off ConvertRealWorld "Real World Value (RWV)" RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Delay DelayLengthSource "Dialog" DelayLength "2" DelayLengthUpperLimit "100" InitialConditionSource "Dialog" InitialCondition "0.0" ExternalReset "None" PreventDirectFeedthrough off DiagnosticForOutOfRangeDelayLength "None" RemoveProtectionDelayLength off InputProcessing "Elements as channels (sample based)" UseCircularBuffer off SampleTime "-1" StateMustResolveToSignalObject off CodeGenStateStorageClass "Auto" } Block { BlockType Demux Outputs "4" DisplayOption "none" BusSelectionMode off } Block { BlockType Display Format "short" Decimation "10" Floating off SampleTime "-1" } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType Goto IconDisplay "Tag" TagVisibility "local" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Product Inputs "2" Multiplication "Element-wise(.*)" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType S-Function FunctionName "system" SFunctionModules "''" PortCounts "[]" SFunctionDeploymentMode off } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" DataFormat "Array" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" SFBlockType "NONE" Variant off GeneratePreprocessorConditionals off } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Switch Criteria "u2 >= Threshold" Threshold "0" InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit via internal rule" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on ZeroCross on SampleTime "-1" AllowDiffInputSizes off } Block { BlockType Terminator } } System { Name "modul_convolution" Location [320, 425, 1691, 1239] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "7024" Block { BlockType Constant Name "Constant1" SID "153" Position [150, 12, 200, 28] ZOrder -4 NamePlacement "alternate" Value "0" OutDataTypeStr "fixdt(0,27,0)" } Block { BlockType Constant Name "Constant10" SID "767" Position [165, 537, 215, 553] ZOrder -4 NamePlacement "alternate" ShowName off OutDataTypeStr "double" } Block { BlockType Constant Name "Constant11" SID "768" Position [165, 567, 215, 583] ZOrder -4 NamePlacement "alternate" ShowName off Value "2" OutDataTypeStr "double" } Block { BlockType Constant Name "Constant2" SID "49" Position [535, 107, 585, 123] ZOrder -4 NamePlacement "alternate" Value "1200" OutDataTypeStr "fixdt(0,27,0)" } Block { BlockType Constant Name "Constant3" SID "154" Position [150, 97, 200, 113] ZOrder -4 NamePlacement "alternate" Value "100" OutDataTypeStr "fixdt(0,27,0)" } Block { BlockType Constant Name "Constant4" SID "178" Position [315, 232, 365, 248] ZOrder -4 NamePlacement "alternate" ShowName off Value "2" OutDataTypeStr "double" } Block { BlockType Constant Name "Constant5" SID "179" Position [315, 257, 365, 273] ZOrder -4 NamePlacement "alternate" ShowName off OutDataTypeStr "double" } Block { BlockType Constant Name "Constant6" SID "205" Position [315, 282, 365, 298] ZOrder -4 NamePlacement "alternate" ShowName off Value "3" OutDataTypeStr "double" } Block { BlockType Constant Name "Constant7" SID "206" Position [315, 307, 365, 323] ZOrder -4 NamePlacement "alternate" ShowName off Value "2" OutDataTypeStr "double" } Block { BlockType Constant Name "Constant8" SID "765" Position [165, 477, 215, 493] ZOrder -4 NamePlacement "alternate" ShowName off Value "2" OutDataTypeStr "double" } Block { BlockType Constant Name "Constant9" SID "766" Position [165, 507, 215, 523] ZOrder -4 NamePlacement "alternate" ShowName off Value "3" OutDataTypeStr "double" } Block { BlockType DataTypeConversion Name "Conversion" SID "146" Position [425, 43, 470, 67] ZOrder 9 OutDataTypeStr "fixdt(0,27,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Display Name "Display1" SID "294" Ports [1] Position [730, 209, 815, 231] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display10" SID "293" Ports [1] Position [730, 184, 815, 206] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display2" SID "295" Ports [1] Position [730, 234, 815, 256] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display3" SID "296" Ports [1] Position [730, 259, 815, 281] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType SubSystem Name "FIR_complex" SID "754" Ports [2, 2] Position [550, 462, 655, 633] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FIR_complex" Location [0, 44, 1817, 1080] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x1_pos" SID "755" Position [25, 28, 55, 42] ZOrder 33 IconDisplay "Port number" } Block { BlockType Inport Name "x2_pos" SID "756" Position [25, 58, 55, 72] ZOrder 33 Port "2" IconDisplay "Port number" } Block { BlockType DataTypeConversion Name "Data Type Conversion" SID "6711" Position [550, 257, 595, 273] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,7,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion1" SID "7014" Position [550, 287, 595, 303] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,7,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType From Name "From" SID "681" Position [515, 31, 580, 49] ZOrder 14 ShowName off GotoTag "x1_pos" } Block { BlockType From Name "From1" SID "7015" Position [435, 256, 500, 274] ZOrder 14 ShowName off GotoTag "x1_pos" } Block { BlockType From Name "From2" SID "7016" Position [435, 288, 500, 302] ZOrder 14 ShowName off GotoTag "x2_pos" } Block { BlockType From Name "From3" SID "696" Position [515, 58, 580, 72] ZOrder 14 ShowName off GotoTag "x2_pos" } Block { BlockType SubSystem Name "modul_fir1" SID "6715" Ports [2, 1] Position [645, 250, 685, 310] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 15 archSelection "Module" Array { Type "Cell" Dimension 4 Cell "InputPipeline" Cell [1.0] Cell "OutputPipeline" Cell [1.0] PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Wmod|P" MaskStyleString "edit,edit" MaskVariables "Wmod=@1;P=@2;" MaskTunableValueString "on,on" MaskCallbackString "|" MaskEnableString "on,on" MaskVisibilityString "on,on" MaskToolTipString "on,on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "7|97" System { Name "modul_fir1" Location [235, 359, 1708, 976] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "in1" SID "6716" Position [140, 33, 170, 47] ZOrder 33 IconDisplay "Port number" } Block { BlockType Inport Name "in2" SID "6717" Position [140, 103, 170, 117] ZOrder 33 Port "2" IconDisplay "Port number" } Block { BlockType Delay Name "Delay1" SID "6718" Ports [1, 1] Position [860, 208, 895, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay10" SID "6719" Ports [1, 1] Position [860, 23, 895, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay11" SID "6720" Ports [1, 1] Position [1005, 23, 1040, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay12" SID "6721" Ports [1, 1] Position [715, 208, 750, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay13" SID "6722" Ports [1, 1] Position [1150, 23, 1185, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay14" SID "6723" Ports [1, 1] Position [1150, 208, 1185, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay2" SID "6724" Ports [1, 1] Position [1005, 208, 1040, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay3" SID "6725" Ports [1, 1] Position [250, 208, 285, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay4" SID "6726" Ports [1, 1] Position [410, 208, 445, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay5" SID "6727" Ports [1, 1] Position [560, 208, 595, 242] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay6" SID "6728" Ports [1, 1] Position [250, 23, 285, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay7" SID "6729" Ports [1, 1] Position [410, 23, 445, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay8" SID "6730" Ports [1, 1] Position [560, 23, 595, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay9" SID "6731" Ports [1, 1] Position [715, 23, 750, 57] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType From Name "From1" SID "6732" Position [35, 381, 100, 399] ZOrder 14 ShowName off GotoTag "c_out" } Block { BlockType From Name "From2" SID "6733" Position [35, 441, 100, 459] ZOrder 14 ShowName off GotoTag "b_delay" } Block { BlockType From Name "From20" SID "6734" Position [35, 321, 100, 339] ZOrder 14 ShowName off GotoTag "a_delay" } Block { BlockType SubSystem Name "Subsystem" SID "6735" Ports [3, 3] Position [210, 301, 290, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 16 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6736" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6737" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6738" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6739" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6740" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6741" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6742" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6743" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6744" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6745" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6746" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6747" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6748" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6749" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6750" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6751" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6752" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6753" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 17 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6754" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 18 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6755" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 19 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6756" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 20 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6757" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 21 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6758" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 22 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6759" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 23 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6760" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 24 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6761" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6762" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6763" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6764" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6765" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6766" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6767" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6768" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6769" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6770" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6771" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay24" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 2 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 1 } } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 2 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay28" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { DstBlock "mult_97lut" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 1 } } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 2 } } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } } } Block { BlockType SubSystem Name "Subsystem1" SID "6772" Ports [3, 3] Position [345, 301, 425, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 25 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem1" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6773" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6774" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6775" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6776" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6777" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6778" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6779" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6780" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6781" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6782" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6783" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6784" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6785" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6786" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6787" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6788" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6789" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6790" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 26 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6791" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 27 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6792" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 28 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6793" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 29 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6794" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 30 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6795" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 31 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6796" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 32 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6797" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 33 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6798" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6799" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6800" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6801" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6802" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6803" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6804" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6805" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6806" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6807" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6808" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut7" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut7" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut" DstPort 1 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut1" DstPort 1 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut2" DstPort 1 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } Branch { DstBlock "Delay28" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut4" DstPort 1 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut6" DstPort 2 } Branch { DstBlock "Delay20" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut6" DstPort 1 } Branch { DstBlock "Delay19" DstPort 1 } } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } Branch { DstBlock "Delay22" DstPort 1 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut1" DstPort 2 } Branch { DstBlock "Delay23" DstPort 1 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut2" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } Branch { DstBlock "Delay18" DstPort 1 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut4" DstPort 2 } Branch { DstBlock "Delay15" DstPort 1 } } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } Branch { DstBlock "Delay21" DstPort 1 } } } } Block { BlockType SubSystem Name "Subsystem2" SID "6809" Ports [3, 3] Position [490, 301, 570, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 34 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem2" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6810" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6811" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6812" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6813" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6814" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6815" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6816" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6817" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6818" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6819" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6820" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6821" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6822" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6823" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6824" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6825" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6826" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6827" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 35 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6828" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 36 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6829" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 37 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6830" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 38 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6831" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 39 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6832" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 40 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6833" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 41 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6834" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 42 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6835" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6836" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6837" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6838" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6839" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6840" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6841" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6842" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6843" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6844" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6845" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay24" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 2 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 1 } } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 2 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay28" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { DstBlock "mult_97lut" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 1 } } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 2 } } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } } } Block { BlockType SubSystem Name "Subsystem3" SID "6846" Ports [3, 3] Position [630, 301, 710, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 43 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem3" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6847" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6848" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6849" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6850" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6851" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6852" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6853" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6854" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6855" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6856" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6857" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6858" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6859" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6860" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6861" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6862" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6863" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6864" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 44 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6865" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 45 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6866" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 46 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6867" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 47 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6868" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 48 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6869" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 49 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6870" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 50 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6871" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 51 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6872" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6873" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6874" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6875" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6876" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6877" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6878" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6879" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6880" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6881" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6882" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut7" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut7" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut" DstPort 1 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut1" DstPort 1 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut2" DstPort 1 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } Branch { DstBlock "Delay28" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut4" DstPort 1 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut6" DstPort 2 } Branch { DstBlock "Delay20" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut6" DstPort 1 } Branch { DstBlock "Delay19" DstPort 1 } } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } Branch { DstBlock "Delay22" DstPort 1 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut1" DstPort 2 } Branch { DstBlock "Delay23" DstPort 1 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut2" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } Branch { DstBlock "Delay18" DstPort 1 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut4" DstPort 2 } Branch { DstBlock "Delay15" DstPort 1 } } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } Branch { DstBlock "Delay21" DstPort 1 } } } } Block { BlockType SubSystem Name "Subsystem4" SID "6883" Ports [3, 3] Position [780, 301, 860, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 52 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem4" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6884" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6885" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6886" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6887" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6888" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6889" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6890" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6891" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6892" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6893" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6894" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6895" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6896" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6897" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6898" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6899" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6900" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6901" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 53 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6902" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 54 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6903" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 55 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6904" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 56 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6905" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 57 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6906" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 58 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6907" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 59 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6908" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 60 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6909" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6910" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6911" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6912" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6913" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6914" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6915" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6916" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6917" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6918" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6919" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay24" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 2 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 1 } } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 2 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay28" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { DstBlock "mult_97lut" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 1 } } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 2 } } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } } } Block { BlockType SubSystem Name "Subsystem5" SID "6920" Ports [3, 3] Position [895, 301, 975, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 61 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem5" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6921" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6922" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6923" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6924" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6925" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6926" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6927" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6928" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6929" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6930" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6931" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6932" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6933" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6934" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6935" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6936" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6937" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6938" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 62 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6939" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 63 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6940" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 64 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6941" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 65 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6942" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 66 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6943" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 67 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6944" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 68 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6945" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 69 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6946" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6947" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6948" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6949" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6950" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6951" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6952" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6953" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6954" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6955" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6956" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut7" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut7" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut" DstPort 1 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut1" DstPort 1 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut2" DstPort 1 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } Branch { DstBlock "Delay28" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut4" DstPort 1 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut6" DstPort 2 } Branch { DstBlock "Delay20" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "mult_97lut6" DstPort 1 } Branch { DstBlock "Delay19" DstPort 1 } } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } Branch { DstBlock "Delay22" DstPort 1 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut1" DstPort 2 } Branch { DstBlock "Delay23" DstPort 1 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut2" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } Branch { DstBlock "Delay18" DstPort 1 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "mult_97lut4" DstPort 2 } Branch { DstBlock "Delay15" DstPort 1 } } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } Branch { DstBlock "Delay21" DstPort 1 } } } } Block { BlockType SubSystem Name "Subsystem6" SID "6957" Ports [3, 3] Position [1040, 301, 1120, 479] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 70 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem6" Location [273, 647, 1663, 918] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6958" Position [35, 38, 65, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6959" Position [170, 168, 200, 182] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6960" Position [25, 223, 55, 237] Port "3" IconDisplay "Port number" } Block { BlockType Delay Name "Delay15" SID "6961" Ports [1, 1] Position [835, 213, 870, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6962" Ports [1, 1] Position [835, 28, 870, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6963" Ports [1, 1] Position [980, 28, 1015, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6964" Ports [1, 1] Position [690, 213, 725, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6965" Ports [1, 1] Position [1125, 28, 1160, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6966" Ports [1, 1] Position [1125, 213, 1160, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6967" Ports [1, 1] Position [980, 213, 1015, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6968" Ports [1, 1] Position [225, 213, 260, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6969" Ports [1, 1] Position [385, 213, 420, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6970" Ports [1, 1] Position [535, 213, 570, 247] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6971" Ports [1, 1] Position [225, 28, 260, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6972" Ports [1, 1] Position [385, 28, 420, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6973" Ports [1, 1] Position [535, 28, 570, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay28" SID "6974" Ports [1, 1] Position [690, 28, 725, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "mult_97lut" SID "6975" Ports [2, 1] Position [100, 84, 145, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 71 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6976" Ports [2, 1] Position [290, 84, 335, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 72 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6977" Ports [2, 1] Position [450, 84, 495, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 73 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6978" Ports [2, 1] Position [605, 84, 650, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 74 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6979" Ports [2, 1] Position [755, 84, 800, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 75 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6980" Ports [2, 1] Position [910, 84, 955, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 76 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "6981" Ports [2, 1] Position [1050, 79, 1095, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 77 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "6982" Ports [2, 1] Position [1195, 84, 1240, 126] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 78 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod10" SID "6983" Ports [2, 1] Position [845, 134, 880, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod11" SID "6984" Ports [2, 1] Position [990, 134, 1025, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod12" SID "6985" Ports [2, 1] Position [1130, 134, 1165, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod13" SID "6986" Ports [2, 1] Position [1275, 134, 1310, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod14" SID "6987" Ports [2, 1] Position [225, 144, 260, 186] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod7" SID "6988" Ports [2, 1] Position [375, 134, 410, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod8" SID "6989" Ports [2, 1] Position [535, 134, 570, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod9" SID "6990" Ports [2, 1] Position [690, 134, 725, 176] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Outport Name "a_delay" SID "6991" Position [1200, 38, 1230, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6992" Position [1335, 148, 1365, 162] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6993" Position [1200, 223, 1230, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "Delay15" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut5" DstPort 2 } } Line { SrcBlock "Delay18" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut3" DstPort 2 } } Line { SrcBlock "Delay23" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay24" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 2 } } Line { SrcBlock "Delay22" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, -115] DstBlock "mult_97lut" DstPort 2 } } Line { SrcBlock "sum_mod11" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod12" DstPort 2 } Line { SrcBlock "sum_mod10" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod11" DstPort 2 } Line { SrcBlock "sum_mod9" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod10" DstPort 2 } Line { SrcBlock "sum_mod8" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod9" DstPort 2 } Line { SrcBlock "sum_mod7" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod8" DstPort 2 } Line { SrcBlock "Delay17" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 1 } } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 2 } } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 45] DstBlock "sum_mod12" DstPort 1 } Line { SrcBlock "Delay16" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 40] DstBlock "sum_mod11" DstPort 1 } Line { SrcBlock "Delay28" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 40] DstBlock "sum_mod10" DstPort 1 } Line { SrcBlock "Delay27" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay28" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 40] DstBlock "sum_mod9" DstPort 1 } Line { SrcBlock "Delay26" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0] DstBlock "sum_mod8" DstPort 1 } Line { SrcBlock "Delay25" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0] DstBlock "sum_mod7" DstPort 1 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { DstBlock "mult_97lut" DstPort 1 } } Line { SrcBlock "sum_mod12" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 1 } } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 2 } } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 40] DstBlock "sum_mod13" DstPort 1 } Line { SrcBlock "sum_mod14" SrcPort 1 DstBlock "sum_mod7" DstPort 2 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [30, 0; 0, 50] DstBlock "sum_mod14" DstPort 1 } Line { SrcBlock "sum_mod13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "sum_mod14" DstPort 2 } } } Block { BlockType Reference Name "mult_97lut" SID "6994" Ports [2, 1] Position [200, 79, 245, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 79 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut1" SID "6995" Ports [2, 1] Position [315, 79, 360, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 80 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut2" SID "6996" Ports [2, 1] Position [475, 79, 520, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 81 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut3" SID "6997" Ports [2, 1] Position [630, 79, 675, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 82 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut4" SID "6998" Ports [2, 1] Position [780, 79, 825, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 83 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut5" SID "6999" Ports [2, 1] Position [930, 79, 975, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 84 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut6" SID "7000" Ports [2, 1] Position [1075, 79, 1120, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 85 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "mult_97lut7" SID "7001" Ports [2, 1] Position [1220, 79, 1265, 121] LibraryVersion "1.40" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 86 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } SourceBlock "resedue_lib/mult_97lut" SourceType "SubSystem" } Block { BlockType Reference Name "sum_mod0" SID "7002" Ports [2, 1] Position [400, 129, 435, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod1" SID "7003" Ports [2, 1] Position [560, 129, 595, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod2" SID "7004" Ports [2, 1] Position [715, 129, 750, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod3" SID "7005" Ports [2, 1] Position [870, 129, 905, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod4" SID "7006" Ports [2, 1] Position [1015, 129, 1050, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod5" SID "7007" Ports [2, 1] Position [1155, 129, 1190, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Reference Name "sum_mod6" SID "7008" Ports [2, 1] Position [1300, 129, 1335, 171] LibraryVersion "1.40" SourceBlock "resedue_lib/sum_mod" SourceType "WIDTH of input value" Wmod "Wmod" P "P" } Block { BlockType Goto Name "to1" SID "7009" Position [1360, 217, 1425, 233] ZOrder 15 ShowName off GotoTag "b_delay" IconDisplay "Signal name" } Block { BlockType Goto Name "to11" SID "7010" Position [1360, 32, 1425, 48] ZOrder 15 ShowName off GotoTag "a_delay" IconDisplay "Signal name" } Block { BlockType Goto Name "to2" SID "7011" Position [1360, 142, 1425, 158] ZOrder 15 ShowName off GotoTag "c_out" IconDisplay "Signal name" } Block { BlockType Outport Name "out" SID "7012" Position [1415, 83, 1445, 97] ZOrder -17 IconDisplay "Port number" } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay12" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Delay12" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "mult_97lut" SrcPort 1 Points [20, 0; 0, 10] Branch { Points [0, 50] DstBlock "sum_mod0" DstPort 2 } Branch { DstBlock "mult_97lut1" DstPort 2 } } Line { SrcBlock "in2" SrcPort 1 Points [10, 0] Branch { Points [0, 115] DstBlock "Delay3" DstPort 1 } Branch { DstBlock "mult_97lut" DstPort 2 } } Line { SrcBlock "sum_mod4" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod5" DstPort 2 } Line { SrcBlock "sum_mod3" SrcPort 1 Points [45, 0; 0, 10] DstBlock "sum_mod4" DstPort 2 } Line { SrcBlock "sum_mod2" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod3" DstPort 2 } Line { SrcBlock "sum_mod1" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod2" DstPort 2 } Line { SrcBlock "sum_mod0" SrcPort 1 Points [55, 0; 0, 10] DstBlock "sum_mod1" DstPort 2 } Line { SrcBlock "Delay11" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay13" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Delay14" DstPort 1 } Line { SrcBlock "mult_97lut6" SrcPort 1 Points [0, 5] Branch { Points [0, 35] DstBlock "sum_mod5" DstPort 1 } Branch { Points [0, 5] DstBlock "mult_97lut7" DstPort 2 } } Line { SrcBlock "Delay10" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay11" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut5" DstPort 1 } } Line { SrcBlock "mult_97lut5" SrcPort 1 Points [0, 10] Branch { Points [0, 30] DstBlock "sum_mod4" DstPort 1 } Branch { DstBlock "mult_97lut6" DstPort 2 } } Line { SrcBlock "Delay9" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay10" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 1 } } Line { SrcBlock "mult_97lut4" SrcPort 1 Points [0, 10] Branch { Points [0, 30] DstBlock "sum_mod3" DstPort 1 } Branch { DstBlock "mult_97lut5" DstPort 2 } } Line { SrcBlock "Delay8" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay9" DstPort 1 } Branch { Points [0, 50] DstBlock "mult_97lut3" DstPort 1 } } Line { SrcBlock "mult_97lut3" SrcPort 1 Points [0, 10] Branch { Points [0, 30] DstBlock "sum_mod2" DstPort 1 } Branch { DstBlock "mult_97lut4" DstPort 2 } } Line { SrcBlock "Delay7" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay8" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 1 } } Line { SrcBlock "mult_97lut2" SrcPort 1 Points [20, 0; 0, 10] Branch { DstBlock "sum_mod1" DstPort 1 } Branch { DstBlock "mult_97lut3" DstPort 2 } } Line { SrcBlock "Delay6" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay7" DstPort 1 } Branch { DstBlock "mult_97lut1" DstPort 1 } } Line { SrcBlock "mult_97lut1" SrcPort 1 Points [20, 0; 0, 10] Branch { DstBlock "sum_mod0" DstPort 1 } Branch { DstBlock "mult_97lut2" DstPort 2 } } Line { SrcBlock "in1" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay6" DstPort 1 } Branch { DstBlock "mult_97lut" DstPort 1 } } Line { SrcBlock "sum_mod5" SrcPort 1 Points [50, 0; 0, 10] DstBlock "sum_mod6" DstPort 2 } Line { SrcBlock "Delay13" SrcPort 1 Points [15, 0] Branch { DstBlock "to11" DstPort 1 } Branch { DstBlock "mult_97lut7" DstPort 1 } } Line { SrcBlock "Delay14" SrcPort 1 DstBlock "to1" DstPort 1 } Line { SrcBlock "mult_97lut7" SrcPort 1 Points [0, 10] Branch { Points [0, 30] DstBlock "sum_mod6" DstPort 1 } Branch { Points [0, -20] DstBlock "out" DstPort 1 } } Line { SrcBlock "sum_mod6" SrcPort 1 DstBlock "to2" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Subsystem" DstPort 2 } Line { Labels [0, 0] SrcBlock "From20" SrcPort 1 DstBlock "Subsystem" DstPort 1 } Line { Labels [0, 0] SrcBlock "From2" SrcPort 1 DstBlock "Subsystem" DstPort 3 } Line { SrcBlock "Subsystem" SrcPort 1 DstBlock "Subsystem1" DstPort 1 } Line { SrcBlock "Subsystem" SrcPort 2 DstBlock "Subsystem1" DstPort 2 } Line { SrcBlock "Subsystem" SrcPort 3 DstBlock "Subsystem1" DstPort 3 } Line { SrcBlock "Subsystem1" SrcPort 1 DstBlock "Subsystem2" DstPort 1 } Line { SrcBlock "Subsystem1" SrcPort 2 DstBlock "Subsystem2" DstPort 2 } Line { SrcBlock "Subsystem1" SrcPort 3 DstBlock "Subsystem2" DstPort 3 } Line { SrcBlock "Subsystem2" SrcPort 1 DstBlock "Subsystem3" DstPort 1 } Line { SrcBlock "Subsystem2" SrcPort 2 DstBlock "Subsystem3" DstPort 2 } Line { SrcBlock "Subsystem2" SrcPort 3 DstBlock "Subsystem3" DstPort 3 } Line { SrcBlock "Subsystem3" SrcPort 1 DstBlock "Subsystem4" DstPort 1 } Line { SrcBlock "Subsystem3" SrcPort 2 DstBlock "Subsystem4" DstPort 2 } Line { SrcBlock "Subsystem3" SrcPort 3 DstBlock "Subsystem4" DstPort 3 } Line { SrcBlock "Subsystem5" SrcPort 1 DstBlock "Subsystem6" DstPort 1 } Line { SrcBlock "Subsystem5" SrcPort 2 DstBlock "Subsystem6" DstPort 2 } Line { SrcBlock "Subsystem5" SrcPort 3 DstBlock "Subsystem6" DstPort 3 } Line { SrcBlock "Subsystem4" SrcPort 1 DstBlock "Subsystem5" DstPort 1 } Line { SrcBlock "Subsystem4" SrcPort 2 DstBlock "Subsystem5" DstPort 2 } Line { SrcBlock "Subsystem4" SrcPort 3 DstBlock "Subsystem5" DstPort 3 } } } Block { BlockType SubSystem Name "posX1X2" SID "2027" Ports [2, 1] Position [615, 35, 715, 90] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 87 archSelection "Module" Array { Type "Cell" Dimension 4 Cell "InputPipeline" Cell [1.0] Cell "OutputPipeline" Cell [1.0] PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "posX1X2" Location [97, 49, 1705, 1076] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "in1_pos" SID "2028" Position [110, 38, 140, 52] ZOrder 33 IconDisplay "Port number" } Block { BlockType Inport Name "in2_pos" SID "2029" Position [110, 108, 140, 122] ZOrder 33 Port "2" IconDisplay "Port number" } Block { BlockType Sum Name "Add" SID "2030" Ports [2, 1] Position [380, 132, 410, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add1" SID "2031" Ports [2, 1] Position [540, 132, 570, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add2" SID "2032" Ports [2, 1] Position [690, 132, 720, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add3" SID "2033" Ports [2, 1] Position [845, 132, 875, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add4" SID "2034" Ports [2, 1] Position [990, 127, 1020, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add5" SID "2035" Ports [2, 1] Position [1135, 127, 1165, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add6" SID "2806" Ports [2, 1] Position [1285, 127, 1315, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion" SID "7017" Position [275, 116, 290, 134] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion1" SID "7018" Position [440, 111, 455, 129] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion2" SID "7019" Position [590, 111, 605, 129] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion3" SID "7020" Position [750, 111, 765, 129] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion4" SID "7021" Position [895, 111, 910, 129] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion5" SID "7022" Position [1040, 111, 1055, 129] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Conversion6" SID "7023" Position [1190, 111, 1205, 129] ZOrder 9 ShowName off OutDataTypeStr "fixdt(0,16,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay" SID "2036" Ports [1, 1] Position [230, 28, 265, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay1" SID "2037" Ports [1, 1] Position [390, 28, 425, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay10" SID "2038" Ports [1, 1] Position [840, 183, 875, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay11" SID "2039" Ports [1, 1] Position [985, 183, 1020, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay12" SID "2807" Ports [1, 1] Position [1135, 183, 1170, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay13" SID "2808" Ports [1, 1] Position [1135, 28, 1170, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay2" SID "2040" Ports [1, 1] Position [540, 28, 575, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay3" SID "2041" Ports [1, 1] Position [695, 28, 730, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay4" SID "2042" Ports [1, 1] Position [840, 28, 875, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay5" SID "2043" Ports [1, 1] Position [985, 28, 1020, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay6" SID "2044" Ports [1, 1] Position [230, 183, 265, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay7" SID "2045" Ports [1, 1] Position [390, 183, 425, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay8" SID "2046" Ports [1, 1] Position [540, 183, 575, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay9" SID "2047" Ports [1, 1] Position [695, 183, 730, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType From Name "From1" SID "2848" Position [65, 371, 130, 389] ZOrder 14 ShowName off GotoTag "bpos1" } Block { BlockType From Name "From2" SID "2850" Position [85, 341, 150, 359] ZOrder 14 ShowName off GotoTag "opos1" } Block { BlockType From Name "From20" SID "2847" Position [65, 306, 130, 324] ZOrder 14 ShowName off GotoTag "apos1" } Block { BlockType Product Name "Product" SID "2048" Ports [2, 1] Position [220, 92, 250, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product1" SID "2049" Ports [2, 1] Position [320, 77, 350, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product2" SID "2050" Ports [2, 1] Position [630, 77, 660, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product3" SID "2051" Ports [2, 1] Position [480, 77, 510, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product4" SID "2052" Ports [2, 1] Position [785, 77, 815, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product5" SID "2053" Ports [2, 1] Position [930, 72, 960, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product6" SID "2054" Ports [2, 1] Position [1075, 72, 1105, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product7" SID "2809" Ports [2, 1] Position [1225, 72, 1255, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType SubSystem Name "Subsystem" SID "2924" Ports [3, 3] Position [205, 307, 265, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 88 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "2925" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "2929" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "2927" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "2818" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "2819" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "2820" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "2821" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "2849" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "2815" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "2816" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "2817" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "2822" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "2823" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "2824" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "2825" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "2826" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "2827" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "2828" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "2829" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "2830" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "2831" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "2832" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "2833" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "2834" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "2835" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "2838" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "2839" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "2840" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "2841" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "2842" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "2843" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "2836" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "2837" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "2926" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "2928" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "2930" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay14" DstPort 1 } Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } } Line { SrcBlock "b" SrcPort 1 Points [15, 0] Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } } } Block { BlockType SubSystem Name "Subsystem1" SID "2931" Ports [3, 3] Position [320, 307, 380, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 89 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem1" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "2932" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "2933" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "2934" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "2935" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "2936" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "2937" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "2938" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "2939" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "2940" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "2941" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "2942" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "2943" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "2944" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "2945" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "2946" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "2947" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "2948" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "2949" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "2950" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "2951" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "2952" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "2953" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "2954" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "2955" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "2956" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "2957" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "2958" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "2959" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "2960" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "2961" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "2962" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "2963" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "2964" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "2965" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "2966" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "2967" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } Branch { DstBlock "Delay18" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, -85] Branch { DstBlock "Delay24" DstPort 1 } Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } Branch { DstBlock "Delay14" DstPort 1 } } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } Branch { DstBlock "Delay19" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } Branch { DstBlock "Delay23" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } Branch { DstBlock "Delay22" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } Branch { DstBlock "Delay21" DstPort 1 } } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } Branch { DstBlock "Delay20" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } Branch { DstBlock "Delay15" DstPort 1 } } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } } } Block { BlockType SubSystem Name "Subsystem2" SID "2968" Ports [3, 3] Position [420, 307, 480, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 90 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem2" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "2969" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "2970" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "2971" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "2972" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "2973" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "2974" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "2975" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "2976" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "2977" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "2978" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "2979" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "2980" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "2981" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "2982" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "2983" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "2984" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "2985" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "2986" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "2987" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "2988" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "2989" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "2990" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "2991" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "2992" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "2993" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "2994" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "2995" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "2996" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "2997" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "2998" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "2999" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "3000" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "3001" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "3002" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "3003" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "3004" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay14" DstPort 1 } Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } } Line { SrcBlock "b" SrcPort 1 Points [15, -85] Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } } } Block { BlockType SubSystem Name "Subsystem3" SID "3005" Ports [3, 3] Position [525, 307, 585, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 91 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem3" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "3006" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "3007" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "3008" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "3009" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "3010" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "3011" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "3012" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "3013" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "3014" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "3015" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "3016" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "3017" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "3018" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "3019" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "3020" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "3021" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "3022" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "3023" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "3024" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "3025" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "3026" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "3027" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "3028" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "3029" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "3030" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "3031" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "3032" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "3033" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "3034" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "3035" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "3036" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "3037" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "3038" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "3039" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "3040" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "3041" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } Branch { DstBlock "Delay18" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, -85] Branch { DstBlock "Delay24" DstPort 1 } Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } Branch { DstBlock "Delay14" DstPort 1 } } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } Branch { DstBlock "Delay19" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } Branch { DstBlock "Delay23" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } Branch { DstBlock "Delay22" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } Branch { DstBlock "Delay21" DstPort 1 } } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } Branch { DstBlock "Delay20" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } Branch { DstBlock "Delay15" DstPort 1 } } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } } } Block { BlockType SubSystem Name "Subsystem4" SID "3042" Ports [3, 3] Position [630, 307, 690, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 92 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem4" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "3043" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "3044" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "3045" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "3046" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "3047" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "3048" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "3049" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "3050" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "3051" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "3052" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "3053" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "3054" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "3055" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "3056" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "3057" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "3058" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "3059" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "3060" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "3061" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "3062" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "3063" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "3064" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "3065" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "3066" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "3067" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "3068" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "3069" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "3070" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "3071" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "3072" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "3073" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "3074" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "3075" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "3076" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "3077" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "3078" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay14" DstPort 1 } Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } } Line { SrcBlock "b" SrcPort 1 Points [15, -85] Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } } } Block { BlockType SubSystem Name "Subsystem5" SID "3079" Ports [3, 3] Position [735, 307, 795, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 93 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem5" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "3080" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "3081" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "3082" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "3083" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "3084" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "3085" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "3086" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "3087" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "3088" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "3089" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "3090" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "3091" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "3092" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "3093" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "3094" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "3095" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "3096" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "3097" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "3098" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "3099" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "3100" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "3101" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "3102" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "3103" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "3104" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "3105" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "3106" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "3107" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "3108" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "3109" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "3110" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "3111" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "3112" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "3113" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "3114" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "3115" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { DstBlock "b_delay" DstPort 1 } Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { DstBlock "a_delay" DstPort 1 } Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } Branch { DstBlock "Delay18" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay17" DstPort 1 } Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay16" DstPort 1 } Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay27" DstPort 1 } Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay26" DstPort 1 } Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay25" DstPort 1 } Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } } Line { SrcBlock "b" SrcPort 1 Points [15, -85] Branch { DstBlock "Delay24" DstPort 1 } Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } Branch { DstBlock "Delay14" DstPort 1 } } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } Branch { DstBlock "Delay19" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } Branch { DstBlock "Delay23" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } Branch { DstBlock "Delay22" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } Branch { DstBlock "Delay21" DstPort 1 } } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } Branch { DstBlock "Delay20" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } Branch { DstBlock "Delay15" DstPort 1 } } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } } } Block { BlockType SubSystem Name "Subsystem6" SID "6674" Ports [3, 3] Position [840, 307, 900, 393] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 94 archSelection "No HDL" } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem6" Location [272, 555, 1587, 796] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "6675" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "c" SID "6676" Position [25, 153, 55, 167] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "6677" Position [25, 193, 55, 207] Port "3" IconDisplay "Port number" } Block { BlockType Sum Name "Add10" SID "6678" Ports [2, 1] Position [765, 132, 795, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add11" SID "6679" Ports [2, 1] Position [910, 127, 940, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add12" SID "6680" Ports [2, 1] Position [1055, 127, 1085, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add13" SID "6681" Ports [2, 1] Position [1205, 127, 1235, 158] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add14" SID "6682" Ports [2, 1] Position [155, 137, 185, 168] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add7" SID "6683" Ports [2, 1] Position [300, 132, 330, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add8" SID "6684" Ports [2, 1] Position [460, 132, 490, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Add9" SID "6685" Ports [2, 1] Position [610, 132, 640, 163] ZOrder -2 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Delay Name "Delay14" SID "6686" Ports [1, 1] Position [150, 28, 185, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay15" SID "6687" Ports [1, 1] Position [310, 28, 345, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay16" SID "6688" Ports [1, 1] Position [760, 183, 795, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay17" SID "6689" Ports [1, 1] Position [905, 183, 940, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay18" SID "6690" Ports [1, 1] Position [1055, 183, 1090, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay19" SID "6691" Ports [1, 1] Position [1055, 28, 1090, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay20" SID "6692" Ports [1, 1] Position [460, 28, 495, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay21" SID "6693" Ports [1, 1] Position [615, 28, 650, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay22" SID "6694" Ports [1, 1] Position [760, 28, 795, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay23" SID "6695" Ports [1, 1] Position [905, 28, 940, 62] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay24" SID "6696" Ports [1, 1] Position [150, 183, 185, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay25" SID "6697" Ports [1, 1] Position [310, 183, 345, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay26" SID "6698" Ports [1, 1] Position [460, 183, 495, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay27" SID "6699" Ports [1, 1] Position [615, 183, 650, 217] ShowName off InputPortMap "u0" DelayLength "1" } Block { BlockType Product Name "Product10" SID "6700" Ports [2, 1] Position [550, 77, 580, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product11" SID "6701" Ports [2, 1] Position [400, 77, 430, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product12" SID "6702" Ports [2, 1] Position [705, 77, 735, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product13" SID "6703" Ports [2, 1] Position [850, 72, 880, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product14" SID "6704" Ports [2, 1] Position [995, 72, 1025, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product15" SID "6705" Ports [2, 1] Position [1145, 72, 1175, 103] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product8" SID "6706" Ports [2, 1] Position [100, 92, 130, 123] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product9" SID "6707" Ports [2, 1] Position [240, 77, 270, 108] ZOrder -19 ShowName off InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "a_delay" SID "6708" Position [1130, 38, 1160, 52] IconDisplay "Port number" } Block { BlockType Outport Name "c_out" SID "6709" Position [1260, 138, 1290, 152] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "b_delay" SID "6710" Position [1135, 193, 1165, 207] Port "3" IconDisplay "Port number" } Line { SrcBlock "Product9" SrcPort 1 Points [10, 0] DstBlock "Add7" DstPort 1 } Line { SrcBlock "Delay14" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay15" DstPort 1 } Branch { Points [0, 40] DstBlock "Product9" DstPort 1 } } Line { SrcBlock "Product11" SrcPort 1 Points [10, 0] DstBlock "Add8" DstPort 1 } Line { SrcBlock "Delay15" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay20" DstPort 1 } Branch { Points [0, 40] DstBlock "Product11" DstPort 1 } } Line { SrcBlock "Add7" SrcPort 1 Points [55, 0; 0, 5] DstBlock "Add8" DstPort 2 } Line { SrcBlock "Product10" SrcPort 1 Points [10, 0] DstBlock "Add9" DstPort 1 } Line { SrcBlock "Delay20" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay21" DstPort 1 } Branch { Points [0, 40] DstBlock "Product10" DstPort 1 } } Line { SrcBlock "Product12" SrcPort 1 Points [10, 0] DstBlock "Add10" DstPort 1 } Line { SrcBlock "Delay21" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay22" DstPort 1 } Branch { Points [0, 40] DstBlock "Product12" DstPort 1 } } Line { SrcBlock "Product13" SrcPort 1 Points [10, 0] DstBlock "Add11" DstPort 1 } Line { SrcBlock "Delay22" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay23" DstPort 1 } Branch { Points [0, 35] DstBlock "Product13" DstPort 1 } } Line { SrcBlock "Product14" SrcPort 1 Points [10, 0] DstBlock "Add12" DstPort 1 } Line { SrcBlock "Delay23" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay19" DstPort 1 } Branch { Points [0, 35] DstBlock "Product14" DstPort 1 } } Line { SrcBlock "Add8" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add9" DstPort 2 } Line { SrcBlock "Add9" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add10" DstPort 2 } Line { SrcBlock "Add10" SrcPort 1 DstBlock "Add11" DstPort 2 } Line { SrcBlock "Add11" SrcPort 1 Points [45, 0; 0, 5] DstBlock "Add12" DstPort 2 } Line { SrcBlock "a" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay14" DstPort 1 } Branch { Points [0, 55] DstBlock "Product8" DstPort 1 } } Line { SrcBlock "b" SrcPort 1 Points [15, -85] Branch { Points [0, -85] DstBlock "Product8" DstPort 2 } Branch { DstBlock "Delay24" DstPort 1 } } Line { SrcBlock "Delay24" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product9" DstPort 2 } Branch { DstBlock "Delay25" DstPort 1 } } Line { SrcBlock "Delay25" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product11" DstPort 2 } Branch { DstBlock "Delay26" DstPort 1 } } Line { SrcBlock "Delay26" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product10" DstPort 2 } Branch { DstBlock "Delay27" DstPort 1 } } Line { SrcBlock "Delay27" SrcPort 1 Points [15, 0] Branch { Points [0, -100] DstBlock "Product12" DstPort 2 } Branch { DstBlock "Delay16" DstPort 1 } } Line { SrcBlock "Delay16" SrcPort 1 Points [15, 0] Branch { Points [0, -105] DstBlock "Product13" DstPort 2 } Branch { DstBlock "Delay17" DstPort 1 } } Line { SrcBlock "Delay17" SrcPort 1 Points [20, 0] Branch { DstBlock "Delay18" DstPort 1 } Branch { Points [0, -105] DstBlock "Product14" DstPort 2 } } Line { SrcBlock "Product15" SrcPort 1 Points [10, 0] DstBlock "Add13" DstPort 1 } Line { SrcBlock "Delay19" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product15" DstPort 1 } Branch { DstBlock "a_delay" DstPort 1 } } Line { SrcBlock "Add12" SrcPort 1 Points [50, 0; 0, 5] DstBlock "Add13" DstPort 2 } Line { SrcBlock "Delay18" SrcPort 1 Points [20, 0] Branch { Points [0, -105] DstBlock "Product15" DstPort 2 } Branch { DstBlock "b_delay" DstPort 1 } } Line { SrcBlock "Add14" SrcPort 1 DstBlock "Add7" DstPort 2 } Line { SrcBlock "Product8" SrcPort 1 Points [5, 0] DstBlock "Add14" DstPort 1 } Line { SrcBlock "Add13" SrcPort 1 DstBlock "c_out" DstPort 1 } Line { SrcBlock "c" SrcPort 1 DstBlock "Add14" DstPort 2 } } } Block { BlockType Goto Name "to1" SID "2811" Position [1320, 192, 1385, 208] ZOrder 15 ShowName off GotoTag "bpos1" IconDisplay "Signal name" } Block { BlockType Goto Name "to11" SID "2810" Position [1320, 37, 1385, 53] ZOrder 15 ShowName off GotoTag "apos1" IconDisplay "Signal name" } Block { BlockType Goto Name "to2" SID "2812" Position [1360, 137, 1425, 153] ZOrder 15 ShowName off GotoTag "opos1" IconDisplay "Signal name" } Block { BlockType Outport Name "out_pos" SID "2055" Position [1440, 83, 1470, 97] ZOrder -17 IconDisplay "Port number" } Line { SrcBlock "Product" SrcPort 1 Points [0, 15] Branch { Points [0, 30] DstBlock "Add" DstPort 2 } Branch { DstBlock "Conversion" DstPort 1 } } Line { SrcBlock "Product1" SrcPort 1 Points [10, 0] DstBlock "Add" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product1" DstPort 1 } Branch { DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Product3" SrcPort 1 Points [10, 0] DstBlock "Add1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product3" DstPort 1 } Branch { DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Add" SrcPort 1 Points [10, 0] Branch { Points [45, 0; 0, 5] DstBlock "Add1" DstPort 2 } Branch { DstBlock "Conversion1" DstPort 1 } } Line { SrcBlock "Product2" SrcPort 1 Points [10, 0] DstBlock "Add2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product2" DstPort 1 } Branch { DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "Product4" SrcPort 1 Points [10, 0] DstBlock "Add3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [15, 0] Branch { Points [0, 40] DstBlock "Product4" DstPort 1 } Branch { DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "Product5" SrcPort 1 Points [10, 0] DstBlock "Add4" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product5" DstPort 1 } Branch { DstBlock "Delay5" DstPort 1 } } Line { SrcBlock "Product6" SrcPort 1 Points [10, 0] DstBlock "Add5" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product6" DstPort 1 } Branch { DstBlock "Delay13" DstPort 1 } } Line { SrcBlock "Add1" SrcPort 1 Points [5, 0] Branch { Points [45, 0; 0, 5] DstBlock "Add2" DstPort 2 } Branch { Points [0, -30] DstBlock "Conversion2" DstPort 1 } } Line { SrcBlock "Add2" SrcPort 1 Points [10, 0] Branch { Points [40, 0; 0, 5] DstBlock "Add3" DstPort 2 } Branch { DstBlock "Conversion3" DstPort 1 } } Line { SrcBlock "Add3" SrcPort 1 Points [10, 0] Branch { DstBlock "Add4" DstPort 2 } Branch { Points [-10, 0] DstBlock "Conversion4" DstPort 1 } } Line { SrcBlock "Add4" SrcPort 1 Points [5, 0] Branch { Points [40, 0; 0, 5] DstBlock "Add5" DstPort 2 } Branch { Points [-5, 0] DstBlock "Conversion5" DstPort 1 } } Line { SrcBlock "in1_pos" SrcPort 1 Points [45, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 55] DstBlock "Product" DstPort 1 } } Line { SrcBlock "in2_pos" SrcPort 1 Points [45, 0] Branch { DstBlock "Product" DstPort 2 } Branch { Points [0, 85] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Delay7" DstPort 1 } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 DstBlock "Delay9" DstPort 1 } Line { SrcBlock "Delay9" SrcPort 1 DstBlock "Delay10" DstPort 1 } Line { SrcBlock "Delay10" SrcPort 1 DstBlock "Delay11" DstPort 1 } Line { SrcBlock "Delay11" SrcPort 1 DstBlock "Delay12" DstPort 1 } Line { SrcBlock "Product7" SrcPort 1 Points [10, 0] DstBlock "Add6" DstPort 1 } Line { SrcBlock "Delay13" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "Product7" DstPort 1 } Branch { DstBlock "to11" DstPort 1 } } Line { SrcBlock "Add5" SrcPort 1 Points [5, 0] Branch { Points [45, 0; 0, 5] DstBlock "Add6" DstPort 2 } Branch { DstBlock "Conversion6" DstPort 1 } } Line { SrcBlock "Delay12" SrcPort 1 DstBlock "to1" DstPort 1 } Line { SrcBlock "Add6" SrcPort 1 Points [20, 0] Branch { DstBlock "to2" DstPort 1 } Branch { Points [0, -55] DstBlock "out_pos" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Subsystem" DstPort 2 } Line { Labels [0, 0] SrcBlock "From20" SrcPort 1 Points [55, 0] DstBlock "Subsystem" DstPort 1 } Line { Labels [0, 0] SrcBlock "From1" SrcPort 1 DstBlock "Subsystem" DstPort 3 } Line { SrcBlock "Subsystem" SrcPort 1 DstBlock "Subsystem1" DstPort 1 } Line { SrcBlock "Subsystem1" SrcPort 1 DstBlock "Subsystem2" DstPort 1 } Line { SrcBlock "Subsystem2" SrcPort 1 DstBlock "Subsystem3" DstPort 1 } Line { SrcBlock "Subsystem3" SrcPort 1 DstBlock "Subsystem4" DstPort 1 } Line { SrcBlock "Subsystem4" SrcPort 1 DstBlock "Subsystem5" DstPort 1 } Line { SrcBlock "Subsystem" SrcPort 2 DstBlock "Subsystem1" DstPort 2 } Line { SrcBlock "Subsystem1" SrcPort 2 DstBlock "Subsystem2" DstPort 2 } Line { SrcBlock "Subsystem2" SrcPort 2 DstBlock "Subsystem3" DstPort 2 } Line { SrcBlock "Subsystem3" SrcPort 2 DstBlock "Subsystem4" DstPort 2 } Line { SrcBlock "Subsystem4" SrcPort 2 DstBlock "Subsystem5" DstPort 2 } Line { SrcBlock "Subsystem" SrcPort 3 DstBlock "Subsystem1" DstPort 3 } Line { SrcBlock "Subsystem1" SrcPort 3 DstBlock "Subsystem2" DstPort 3 } Line { SrcBlock "Subsystem2" SrcPort 3 DstBlock "Subsystem3" DstPort 3 } Line { SrcBlock "Subsystem3" SrcPort 3 DstBlock "Subsystem4" DstPort 3 } Line { SrcBlock "Subsystem4" SrcPort 3 DstBlock "Subsystem5" DstPort 3 } Line { SrcBlock "Subsystem5" SrcPort 1 DstBlock "Subsystem6" DstPort 1 } Line { SrcBlock "Subsystem5" SrcPort 2 DstBlock "Subsystem6" DstPort 2 } Line { SrcBlock "Subsystem5" SrcPort 3 DstBlock "Subsystem6" DstPort 3 } Line { SrcBlock "Conversion" SrcPort 1 Points [10, 0] DstBlock "Product1" DstPort 2 } Line { SrcBlock "Conversion1" SrcPort 1 Points [0, -20] DstBlock "Product3" DstPort 2 } Line { SrcBlock "Conversion2" SrcPort 1 Points [5, 0] DstBlock "Product2" DstPort 2 } Line { SrcBlock "Conversion3" SrcPort 1 Points [10, 0; 0, -20] DstBlock "Product4" DstPort 2 } Line { SrcBlock "Conversion4" SrcPort 1 Points [10, 0; 0, -25] DstBlock "Product5" DstPort 2 } Line { SrcBlock "Conversion5" SrcPort 1 DstBlock "Product6" DstPort 2 } Line { SrcBlock "Conversion6" SrcPort 1 Points [10, 0; 0, -25] DstBlock "Product7" DstPort 2 } } } Block { BlockType Goto Name "to" SID "684" Position [95, 57, 160, 73] ZOrder 15 ShowName off GotoTag "x2_pos" IconDisplay "Signal name" } Block { BlockType Goto Name "to11" SID "695" Position [95, 27, 160, 43] ZOrder 15 ShowName off GotoTag "x1_pos" IconDisplay "Signal name" } Block { BlockType Outport Name "out_posX" SID "758" Position [850, 58, 880, 72] ZOrder -17 IconDisplay "Port number" } Block { BlockType Outport Name "out_mod" SID "7013" Position [790, 273, 820, 287] ZOrder -17 Port "2" IconDisplay "Port number" } Line { SrcBlock "x1_pos" SrcPort 1 DstBlock "to11" DstPort 1 } Line { SrcBlock "x2_pos" SrcPort 1 DstBlock "to" DstPort 1 } Line { SrcBlock "posX1X2" SrcPort 1 DstBlock "out_posX" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [15, 0] DstBlock "posX1X2" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [15, 0] DstBlock "posX1X2" DstPort 2 } Line { SrcBlock "modul_fir1" SrcPort 1 DstBlock "out_mod" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "modul_fir1" DstPort 1 } Line { SrcBlock "Data Type Conversion1" SrcPort 1 DstBlock "modul_fir1" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Data Type Conversion1" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "142" Ports [3] Position [870, 43, 910, 127] ZOrder 5 Floating off Location [195, 345, 669, 851] Open off NumInputPorts "3" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "x|none|none|none|none|none" } ShowLegends off TimeRange "100" YMin "0~0~0" YMax "15000~15000~100" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Scope Name "Scope1" SID "753" Ports [4] Position [925, 445, 960, 615] ZOrder 5 Floating off Location [53, 284, 527, 790] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "x|none|none|none|none|none" } ShowLegends off TimeRange "500" YMin "0~0~0~0" YMax "30~60~30~60" SaveName "ScopeData1" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Step Name "Step" SID "145" Position [120, 45, 150, 75] ZOrder 8 Time "50" SampleTime "0" } Block { BlockType Switch Name "Switch" SID "152" Position [270, 40, 320, 80] ZOrder -18 Criteria "u2 > Threshold" InputSameDT off SaturateOnIntegerOverflow off } Block { BlockType SubSystem Name "complex" SID "172" Ports [4, 8] Position [550, 210, 615, 390] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm|P2|P2Q" MaskStyleString "edit,edit,edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;P2=@6;P2Q=@7;" MaskTunableValueString "on,on,on,on,on,on,on" MaskCallbackString "||||||" MaskEnableString "on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "8|8|97|22|75|0|0" System { Name "complex" Location [237, 49, 1813, 1076] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x1" SID "276" Position [90, 53, 120, 67] ZOrder -1 IconDisplay "Port number" } Block { BlockType Inport Name "y1" SID "277" Position [90, 103, 120, 117] ZOrder -1 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x2" SID "287" Position [90, 198, 120, 212] ZOrder -1 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "y2" SID "288" Position [90, 248, 120, 262] ZOrder -1 Port "4" IconDisplay "Port number" } Block { BlockType Display Name "Display" SID "182" Ports [1] Position [440, 29, 530, 51] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "183" Ports [1] Position [440, 114, 530, 136] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display10" SID "247" Ports [1] Position [885, 460, 975, 490] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display11" SID "248" Ports [1] Position [885, 510, 975, 540] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display12" SID "249" Ports [1] Position [885, 595, 975, 625] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display13" SID "250" Ports [1] Position [885, 665, 975, 695] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display14" SID "342" Ports [1] Position [490, 759, 585, 781] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display15" SID "343" Ports [1] Position [490, 824, 585, 846] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display16" SID "344" Ports [1] Position [490, 889, 585, 911] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display17" SID "345" Ports [1] Position [490, 954, 585, 976] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display2" SID "190" Ports [1] Position [690, 47, 780, 73] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display3" SID "191" Ports [1] Position [690, 97, 780, 123] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display4" SID "207" Ports [1] Position [385, 180, 475, 200] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display5" SID "208" Ports [1] Position [385, 259, 480, 281] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display6" SID "219" Ports [1] Position [420, 470, 510, 500] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display7" SID "220" Ports [1] Position [415, 520, 505, 550] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display8" SID "221" Ports [1] Position [425, 620, 515, 650] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display9" SID "222" Ports [1] Position [420, 670, 510, 700] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From" SID "195" Position [140, 461, 180, 479] ZOrder -9 ShowName off GotoTag "v1" } Block { BlockType From Name "From1" SID "196" Position [140, 485, 180, 505] ZOrder -9 ShowName off GotoTag "v1_" } Block { BlockType From Name "From10" SID "306" Position [235, 806, 275, 824] ZOrder -9 ShowName off GotoTag "y1" } Block { BlockType From Name "From11" SID "307" Position [235, 826, 275, 844] ZOrder -9 ShowName off GotoTag "y2" } Block { BlockType From Name "From12" SID "310" Position [165, 846, 205, 864] ZOrder -9 ShowName off GotoTag "x1" } Block { BlockType From Name "From13" SID "311" Position [165, 866, 205, 884] ZOrder -9 ShowName off GotoTag "x2" } Block { BlockType From Name "From14" SID "312" Position [165, 886, 205, 904] ZOrder -9 ShowName off GotoTag "y1" } Block { BlockType From Name "From15" SID "313" Position [165, 906, 205, 924] ZOrder -9 ShowName off GotoTag "y2" } Block { BlockType From Name "From16" SID "317" Position [185, 926, 225, 944] ZOrder -9 ShowName off GotoTag "x1" } Block { BlockType From Name "From17" SID "318" Position [185, 946, 225, 964] ZOrder -9 ShowName off GotoTag "y2" } Block { BlockType From Name "From18" SID "319" Position [185, 966, 225, 984] ZOrder -9 ShowName off GotoTag "y1" } Block { BlockType From Name "From19" SID "320" Position [185, 986, 225, 1004] ZOrder -9 ShowName off GotoTag "x2" } Block { BlockType From Name "From2" SID "217" Position [135, 511, 175, 529] ZOrder -9 ShowName off GotoTag "v2" } Block { BlockType From Name "From3" SID "218" Position [135, 535, 175, 555] ZOrder -9 ShowName off GotoTag "v2_" } Block { BlockType From Name "From4" SID "223" Position [145, 611, 185, 629] ZOrder -9 ShowName off GotoTag "v1" } Block { BlockType From Name "From5" SID "224" Position [145, 635, 185, 655] ZOrder -9 ShowName off GotoTag "v1_" } Block { BlockType From Name "From6" SID "225" Position [140, 661, 180, 679] ZOrder -9 ShowName off GotoTag "v2" } Block { BlockType From Name "From7" SID "226" Position [140, 685, 180, 705] ZOrder -9 ShowName off GotoTag "v2_" } Block { BlockType From Name "From8" SID "303" Position [235, 766, 275, 784] ZOrder -9 ShowName off GotoTag "x1" } Block { BlockType From Name "From9" SID "304" Position [235, 786, 275, 804] ZOrder -9 ShowName off GotoTag "x2" } Block { BlockType Goto Name "Goto" SID "192" Position [360, 31, 400, 49] ZOrder -10 ShowName off GotoTag "v1" } Block { BlockType Goto Name "Goto1" SID "194" Position [360, 116, 400, 134] ZOrder -10 ShowName off GotoTag "v1_" } Block { BlockType Goto Name "Goto2" SID "209" Position [510, 196, 550, 214] ZOrder -10 ShowName off GotoTag "v2" } Block { BlockType Goto Name "Goto3" SID "210" Position [510, 246, 550, 264] ZOrder -10 ShowName off GotoTag "v2_" } Block { BlockType Goto Name "Goto4" SID "297" Position [180, 41, 220, 59] ZOrder -10 ShowName off GotoTag "x1" } Block { BlockType Goto Name "Goto5" SID "298" Position [180, 116, 220, 134] ZOrder -10 ShowName off GotoTag "y1" } Block { BlockType Goto Name "Goto6" SID "299" Position [170, 181, 210, 199] ZOrder -10 ShowName off GotoTag "x2" } Block { BlockType Goto Name "Goto7" SID "300" Position [170, 261, 210, 279] ZOrder -10 ShowName off GotoTag "y2" } Block { BlockType SubSystem Name "forwardReIm" SID "162" Ports [2, 2] Position [240, 34, 300, 136] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm" System { Name "forwardReIm" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Re" SID "163" Position [100, 243, 130, 257] IconDisplay "Port number" } Block { BlockType Inport Name "Im" SID "168" Position [100, 288, 130, 302] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "forward" SID "164" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "forward" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "40" Block { BlockType Inport Name "x" SID "164::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "y" SID "164::40" Position [20, 136, 40, 154] ZOrder 27 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "164::32" Ports [1, 1] Position [270, 265, 320, 305] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "164::31" Tag "Stateflow S-Function modul_convolution 1" Ports [2, 3] Position [180, 117, 230, 263] ZOrder 18 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[2 3]" EnableBusSupport on Port { PortNumber 2 Name "v" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "v_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "164::34" Position [460, 276, 480, 294] ZOrder 21 } Block { BlockType Outport Name "v" SID "164::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Block { BlockType Outport Name "v_" SID "164::29" Position [460, 136, 480, 154] ZOrder 16 Port "2" IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "v_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "v_" DstPort 1 } Line { Name "v" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "v" DstPort 1 } Line { SrcBlock "y" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "x" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "v" SID "169" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "v_" SID "166" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "forward" SrcPort 2 DstBlock "v_" DstPort 1 } Line { SrcBlock "forward" SrcPort 1 Points [50, 0; 0, -15] DstBlock "v" DstPort 1 } Line { SrcBlock "Re" SrcPort 1 Points [80, 0] DstBlock "forward" DstPort 1 } Line { SrcBlock "Im" SrcPort 1 Points [40, 0; 0, -20] DstBlock "forward" DstPort 2 } } } Block { BlockType SubSystem Name "forwardReIm1" SID "211" Ports [2, 2] Position [240, 179, 300, 281] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm" System { Name "forwardReIm1" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Re" SID "212" Position [100, 243, 130, 257] IconDisplay "Port number" } Block { BlockType Inport Name "Im" SID "213" Position [100, 288, 130, 302] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "forward" SID "214" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "forward" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "40" Block { BlockType Inport Name "x" SID "214::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "y" SID "214::40" Position [20, 136, 40, 154] ZOrder 27 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "214::32" Ports [1, 1] Position [270, 265, 320, 305] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "214::31" Tag "Stateflow S-Function modul_convolution 4" Ports [2, 3] Position [180, 117, 230, 263] ZOrder 18 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[2 3]" EnableBusSupport on Port { PortNumber 2 Name "v" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "v_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "214::34" Position [460, 276, 480, 294] ZOrder 21 } Block { BlockType Outport Name "v" SID "214::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Block { BlockType Outport Name "v_" SID "214::29" Position [460, 136, 480, 154] ZOrder 16 Port "2" IconDisplay "Port number" } Line { SrcBlock "x" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "y" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "v" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "v" DstPort 1 } Line { Name "v_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "v_" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "v" SID "215" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "v_" SID "216" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "Im" SrcPort 1 Points [40, 0; 0, -20] DstBlock "forward" DstPort 2 } Line { SrcBlock "Re" SrcPort 1 Points [80, 0] DstBlock "forward" DstPort 1 } Line { SrcBlock "forward" SrcPort 1 Points [50, 0; 0, -15] DstBlock "v" DstPort 1 } Line { SrcBlock "forward" SrcPort 2 DstBlock "v_" DstPort 1 } } } Block { BlockType SubSystem Name "multReIm" SID "227" Ports [4, 2] Position [285, 606, 345, 709] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm" System { Name "multReIm" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v1" SID "228" Position [50, 218, 80, 232] IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "229" Position [50, 248, 80, 262] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "230" Position [55, 273, 85, 287] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "231" Position [55, 303, 85, 317] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "mult" SID "232" Ports [4, 2] Position [230, 232, 300, 293] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "mult" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "47" Block { BlockType Inport Name "v1" SID "232::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "232::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "232::46" Position [20, 171, 40, 189] ZOrder 33 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "232::47" Position [20, 206, 40, 224] ZOrder 34 Port "4" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "232::32" Ports [1, 1] Position [270, 280, 320, 320] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "232::31" Tag "Stateflow S-Function modul_convolution 5" Ports [4, 3] Position [180, 127, 230, 278] ZOrder 18 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[4 3]" EnableBusSupport on Port { PortNumber 2 Name "sumv" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "sumv_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "232::34" Position [460, 291, 480, 309] ZOrder 21 } Block { BlockType Outport Name "sumv" SID "232::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "232::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "sumv_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "sumv_" DstPort 1 } Line { Name "sumv" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "sumv" DstPort 1 } Line { SrcBlock "v2_" SrcPort 1 DstBlock " SFunction " DstPort 4 } Line { SrcBlock "v2" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "v1_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v1" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "sumv" SID "233" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "234" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "v2_" SrcPort 1 Points [60, 0; 0, -25] DstBlock "mult" DstPort 4 } Line { SrcBlock "v2" SrcPort 1 Points [60, 0; 0, -10] DstBlock "mult" DstPort 3 } Line { SrcBlock "mult" SrcPort 1 Points [50, 0; 0, -20] DstBlock "sumv" DstPort 1 } Line { SrcBlock "v1" SrcPort 1 Points [130, 0] DstBlock "mult" DstPort 1 } Line { SrcBlock "v1_" SrcPort 1 DstBlock "mult" DstPort 2 } Line { SrcBlock "mult" SrcPort 2 Points [0, -5] DstBlock "sumv_" DstPort 1 } } } Block { BlockType SubSystem Name "position" SID "325" Ports [12, 4] Position [355, 755, 440, 1015] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "position" Location [928, 748, 1193, 1075] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "326" Position [25, 38, 55, 52] IconDisplay "Port number" } Block { BlockType Inport Name "In2" SID "328" Position [25, 48, 55, 62] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In3" SID "329" Position [25, 88, 55, 102] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "In4" SID "331" Position [25, 98, 55, 112] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "In5" SID "332" Position [25, 143, 55, 157] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "In6" SID "333" Position [25, 158, 55, 172] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "In7" SID "335" Position [25, 183, 55, 197] Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "In8" SID "336" Position [25, 198, 55, 212] Port "8" IconDisplay "Port number" } Block { BlockType Inport Name "In9" SID "337" Position [25, 233, 55, 247] Port "9" IconDisplay "Port number" } Block { BlockType Inport Name "In10" SID "338" Position [25, 248, 55, 262] Port "10" IconDisplay "Port number" } Block { BlockType Inport Name "In11" SID "340" Position [25, 273, 55, 287] Port "11" IconDisplay "Port number" } Block { BlockType Inport Name "In12" SID "341" Position [25, 288, 55, 302] Port "12" IconDisplay "Port number" } Block { BlockType Product Name "Product" SID "301" Ports [2, 1] Position [80, 142, 110, 173] ZOrder -13 ShowName off InputSameDT off SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product1" SID "314" Ports [2, 1] Position [80, 182, 110, 213] ZOrder -13 ShowName off InputSameDT off SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product2" SID "321" Ports [2, 1] Position [80, 232, 110, 263] ZOrder -13 ShowName off InputSameDT off SaturateOnIntegerOverflow off } Block { BlockType Product Name "Product3" SID "322" Ports [2, 1] Position [80, 272, 110, 303] ZOrder -13 ShowName off InputSameDT off SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum" SID "302" Ports [2, 1] Position [80, 32, 115, 68] ZOrder -18 ShowName off Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum1" SID "308" Ports [2, 1] Position [80, 82, 115, 118] ZOrder -18 ShowName off Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum2" SID "315" Ports [2, 1] Position [150, 157, 185, 193] ZOrder -18 ShowName off Inputs "|+-" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum3" SID "323" Ports [2, 1] Position [150, 247, 185, 283] ZOrder -18 ShowName off Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "Out1" SID "327" Position [140, 38, 170, 52] IconDisplay "Port number" } Block { BlockType Outport Name "Out2" SID "330" Position [140, 88, 170, 102] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out3" SID "334" Position [210, 163, 240, 177] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Out4" SID "339" Position [210, 253, 240, 267] Port "4" IconDisplay "Port number" } Line { SrcBlock "Product" SrcPort 1 Points [10, 0; 0, 10] DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Product1" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Sum2" DstPort 2 } Line { SrcBlock "Product2" SrcPort 1 Points [10, 0; 0, 10] DstBlock "Sum3" DstPort 1 } Line { SrcBlock "Product3" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Sum3" DstPort 2 } Line { SrcBlock "In1" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Sum" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "In2" SrcPort 1 Points [5, 0] DstBlock "Sum" DstPort 2 } Line { SrcBlock "In3" SrcPort 1 DstBlock "Sum1" DstPort 1 } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "In4" SrcPort 1 Points [5, 0] DstBlock "Sum1" DstPort 2 } Line { SrcBlock "In5" SrcPort 1 DstBlock "Product" DstPort 1 } Line { SrcBlock "In6" SrcPort 1 DstBlock "Product" DstPort 2 } Line { SrcBlock "Sum2" SrcPort 1 DstBlock "Out3" DstPort 1 } Line { SrcBlock "In7" SrcPort 1 DstBlock "Product1" DstPort 1 } Line { SrcBlock "In8" SrcPort 1 DstBlock "Product1" DstPort 2 } Line { SrcBlock "In9" SrcPort 1 DstBlock "Product2" DstPort 1 } Line { SrcBlock "In10" SrcPort 1 DstBlock "Product2" DstPort 2 } Line { SrcBlock "Sum3" SrcPort 1 DstBlock "Out4" DstPort 1 } Line { SrcBlock "In11" SrcPort 1 DstBlock "Product3" DstPort 1 } Line { SrcBlock "In12" SrcPort 1 DstBlock "Product3" DstPort 2 } } } Block { BlockType SubSystem Name "reverseReIm" SID "184" Ports [2, 2] Position [555, 34, 615, 136] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm|P2|P2Q" MaskStyleString "edit,edit,edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;P2=@6;P2Q=@7;" MaskTunableValueString "on,on,on,on,on,on,on" MaskCallbackString "||||||" MaskEnableString "on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm|49|86" System { Name "reverseReIm" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v" SID "185" Position [100, 238, 130, 252] IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "186" Position [100, 268, 130, 282] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "reverse" SID "187" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "reverse" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "45" Block { BlockType Inport Name "v" SID "187::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "187::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "187::32" Ports [1, 1] Position [270, 275, 320, 315] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "187::31" Tag "Stateflow S-Function modul_convolution 2" Ports [2, 3] Position [180, 125, 230, 275] ZOrder 18 FunctionName "sf_sfun" Parameters "P,P2,P2Q,Wmod" PortCounts "[2 3]" EnableBusSupport on Port { PortNumber 2 Name "Re" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Im" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "187::34" Position [460, 286, 480, 304] ZOrder 21 } Block { BlockType Outport Name "Re" SID "187::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "187::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock "v" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "Re" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "Re" DstPort 1 } Line { Name "Im" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "Im" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "Re" SID "188" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "189" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "reverse" SrcPort 1 Points [50, 0; 0, -15] DstBlock "Re" DstPort 1 } Line { SrcBlock "v" SrcPort 1 DstBlock "reverse" DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock "reverse" DstPort 2 } Line { SrcBlock "reverse" SrcPort 2 DstBlock "Im" DstPort 1 } } } Block { BlockType SubSystem Name "reverseReIm1" SID "251" Ports [2, 2] Position [625, 449, 685, 551] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm|P2|P2Q" MaskStyleString "edit,edit,edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;P2=@6;P2Q=@7;" MaskTunableValueString "on,on,on,on,on,on,on" MaskCallbackString "||||||" MaskEnableString "on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm|49|86" System { Name "reverseReIm1" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v" SID "252" Position [100, 238, 130, 252] IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "253" Position [100, 268, 130, 282] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "reverse" SID "254" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "reverse" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "45" Block { BlockType Inport Name "v" SID "254::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "254::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "254::32" Ports [1, 1] Position [270, 275, 320, 315] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "254::31" Tag "Stateflow S-Function modul_convolution 6" Ports [2, 3] Position [180, 125, 230, 275] ZOrder 18 FunctionName "sf_sfun" Parameters "P,P2,P2Q,Wmod" PortCounts "[2 3]" EnableBusSupport on Port { PortNumber 2 Name "Re" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Im" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "254::34" Position [460, 286, 480, 304] ZOrder 21 } Block { BlockType Outport Name "Re" SID "254::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "254::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "Im" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "Im" DstPort 1 } Line { Name "Re" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "Re" DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "Re" SID "255" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "256" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "reverse" SrcPort 2 DstBlock "Im" DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock "reverse" DstPort 2 } Line { SrcBlock "v" SrcPort 1 DstBlock "reverse" DstPort 1 } Line { SrcBlock "reverse" SrcPort 1 Points [50, 0; 0, -15] DstBlock "Re" DstPort 1 } } } Block { BlockType SubSystem Name "reverseReIm2" SID "257" Ports [2, 2] Position [625, 584, 685, 686] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm|P2|P2Q" MaskStyleString "edit,edit,edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;P2=@6;P2Q=@7;" MaskTunableValueString "on,on,on,on,on,on,on" MaskCallbackString "||||||" MaskEnableString "on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm|49|86" System { Name "reverseReIm2" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v" SID "258" Position [100, 238, 130, 252] IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "259" Position [100, 268, 130, 282] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "reverse" SID "260" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "reverse" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "45" Block { BlockType Inport Name "v" SID "260::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "260::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "260::32" Ports [1, 1] Position [270, 275, 320, 315] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "260::31" Tag "Stateflow S-Function modul_convolution 7" Ports [2, 3] Position [180, 125, 230, 275] ZOrder 18 FunctionName "sf_sfun" Parameters "P,P2,P2Q,Wmod" PortCounts "[2 3]" EnableBusSupport on Port { PortNumber 2 Name "Re" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Im" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "260::34" Position [460, 286, 480, 304] ZOrder 21 } Block { BlockType Outport Name "Re" SID "260::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "260::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock "v" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "Re" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "Re" DstPort 1 } Line { Name "Im" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "Im" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "Re" SID "261" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "262" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "reverse" SrcPort 1 Points [50, 0; 0, -15] DstBlock "Re" DstPort 1 } Line { SrcBlock "v" SrcPort 1 DstBlock "reverse" DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock "reverse" DstPort 2 } Line { SrcBlock "reverse" SrcPort 2 DstBlock "Im" DstPort 1 } } } Block { BlockType SubSystem Name "sumReIm" SID "197" Ports [4, 2] Position [280, 456, 340, 559] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm" System { Name "sumReIm" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v1" SID "198" Position [50, 218, 80, 232] IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "199" Position [50, 248, 80, 262] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "203" Position [55, 273, 85, 287] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "204" Position [55, 303, 85, 317] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "sum" SID "200" Ports [4, 2] Position [230, 232, 300, 293] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('p" "rivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "sum" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "47" Block { BlockType Inport Name "v1" SID "200::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "200::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "200::46" Position [20, 171, 40, 189] ZOrder 33 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "200::47" Position [20, 206, 40, 224] ZOrder 34 Port "4" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "200::32" Ports [1, 1] Position [270, 280, 320, 320] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "200::31" Tag "Stateflow S-Function modul_convolution 3" Ports [4, 3] Position [180, 127, 230, 278] ZOrder 18 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[4 3]" EnableBusSupport on Port { PortNumber 2 Name "sumv" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "sumv_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "200::34" Position [460, 291, 480, 309] ZOrder 21 } Block { BlockType Outport Name "sumv" SID "200::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "200::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock "v1" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "v1_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v2" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "v2_" SrcPort 1 DstBlock " SFunction " DstPort 4 } Line { Name "sumv" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "sumv" DstPort 1 } Line { Name "sumv_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "sumv_" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "sumv" SID "201" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "202" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "sum" SrcPort 2 Points [0, -5] DstBlock "sumv_" DstPort 1 } Line { SrcBlock "v1_" SrcPort 1 DstBlock "sum" DstPort 2 } Line { SrcBlock "v1" SrcPort 1 Points [130, 0] DstBlock "sum" DstPort 1 } Line { SrcBlock "sum" SrcPort 1 Points [50, 0; 0, -20] DstBlock "sumv" DstPort 1 } Line { SrcBlock "v2" SrcPort 1 Points [60, 0; 0, -10] DstBlock "sum" DstPort 3 } Line { SrcBlock "v2_" SrcPort 1 Points [60, 0; 0, -25] DstBlock "sum" DstPort 4 } } } Block { BlockType Outport Name "xsum" SID "289" Position [780, 483, 810, 497] ZOrder -9 IconDisplay "Port number" } Block { BlockType Outport Name "ysum" SID "290" Position [785, 538, 815, 552] ZOrder -9 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "xmult" SID "291" Position [785, 628, 815, 642] ZOrder -9 Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "ymult" SID "292" Position [785, 698, 815, 712] ZOrder -9 Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "xsum_pos" SID "305" Position [595, 783, 625, 797] ZOrder -9 Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "ysum_pos" SID "309" Position [595, 848, 625, 862] ZOrder -9 Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "xmult_pos" SID "316" Position [595, 913, 625, 927] ZOrder -9 Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "xmult_pos1" SID "324" Position [595, 978, 625, 992] ZOrder -9 Port "8" IconDisplay "Port number" } Line { SrcBlock "reverseReIm1" SrcPort 1 Points [70, 0] Branch { DstBlock "Display10" DstPort 1 } Branch { Points [0, 15] DstBlock "xsum" DstPort 1 } } Line { SrcBlock "reverseReIm1" SrcPort 2 Points [70, 0] Branch { DstBlock "Display11" DstPort 1 } Branch { Points [0, 20] DstBlock "ysum" DstPort 1 } } Line { SrcBlock "reverseReIm2" SrcPort 1 Points [75, 0] Branch { DstBlock "Display12" DstPort 1 } Branch { Points [0, 25] DstBlock "xmult" DstPort 1 } } Line { SrcBlock "reverseReIm2" SrcPort 2 Points [0, 20; 75, 0] Branch { DstBlock "Display13" DstPort 1 } Branch { Points [0, 25] DstBlock "ymult" DstPort 1 } } Line { SrcBlock "multReIm" SrcPort 2 Points [35, 0] Branch { DstBlock "Display9" DstPort 1 } Branch { Points [0, -25] DstBlock "reverseReIm2" DstPort 2 } } Line { SrcBlock "multReIm" SrcPort 1 Points [35, 0] Branch { DstBlock "Display8" DstPort 1 } Branch { Points [0, -20; 225, 0] DstBlock "reverseReIm2" DstPort 1 } } Line { SrcBlock "From7" SrcPort 1 DstBlock "multReIm" DstPort 4 } Line { SrcBlock "From6" SrcPort 1 DstBlock "multReIm" DstPort 3 } Line { SrcBlock "From5" SrcPort 1 DstBlock "multReIm" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "multReIm" DstPort 1 } Line { SrcBlock "sumReIm" SrcPort 2 Points [35, 0] Branch { DstBlock "Display7" DstPort 1 } Branch { Points [0, -10] DstBlock "reverseReIm1" DstPort 2 } } Line { SrcBlock "sumReIm" SrcPort 1 Points [35, 0] Branch { DstBlock "Display6" DstPort 1 } Branch { Points [0, -10] DstBlock "reverseReIm1" DstPort 1 } } Line { SrcBlock "From3" SrcPort 1 DstBlock "sumReIm" DstPort 4 } Line { SrcBlock "From2" SrcPort 1 DstBlock "sumReIm" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 DstBlock "sumReIm" DstPort 2 } Line { SrcBlock "From" SrcPort 1 DstBlock "sumReIm" DstPort 1 } Line { SrcBlock "forwardReIm1" SrcPort 2 Points [40, 0] Branch { DstBlock "Goto3" DstPort 1 } Branch { Points [0, 15] DstBlock "Display5" DstPort 1 } } Line { SrcBlock "forwardReIm1" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, -15] DstBlock "Display4" DstPort 1 } } Line { SrcBlock "reverseReIm" SrcPort 2 DstBlock "Display3" DstPort 1 } Line { SrcBlock "reverseReIm" SrcPort 1 DstBlock "Display2" DstPort 1 } Line { SrcBlock "forwardReIm" SrcPort 2 Points [40, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [80, 0] Branch { DstBlock "reverseReIm" DstPort 2 } Branch { DstBlock "Display1" DstPort 1 } } } Line { SrcBlock "forwardReIm" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [80, 0] Branch { DstBlock "reverseReIm" DstPort 1 } Branch { DstBlock "Display" DstPort 1 } } } Line { SrcBlock "x1" SrcPort 1 Points [35, 0] Branch { DstBlock "forwardReIm" DstPort 1 } Branch { Points [0, -10] DstBlock "Goto4" DstPort 1 } } Line { SrcBlock "y1" SrcPort 1 Points [35, 0] Branch { DstBlock "forwardReIm" DstPort 2 } Branch { Points [0, 15] DstBlock "Goto5" DstPort 1 } } Line { SrcBlock "x2" SrcPort 1 Points [25, 0] Branch { DstBlock "forwardReIm1" DstPort 1 } Branch { Points [0, -15] DstBlock "Goto6" DstPort 1 } } Line { SrcBlock "y2" SrcPort 1 Points [25, 0] Branch { DstBlock "forwardReIm1" DstPort 2 } Branch { Points [0, 15] DstBlock "Goto7" DstPort 1 } } Line { SrcBlock "From8" SrcPort 1 DstBlock "position" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "position" DstPort 2 } Line { SrcBlock "position" SrcPort 1 Points [30, 0] Branch { DstBlock "xsum_pos" DstPort 1 } Branch { DstBlock "Display14" DstPort 1 } } Line { SrcBlock "From10" SrcPort 1 DstBlock "position" DstPort 3 } Line { SrcBlock "From11" SrcPort 1 DstBlock "position" DstPort 4 } Line { SrcBlock "position" SrcPort 2 Points [30, 0] Branch { DstBlock "ysum_pos" DstPort 1 } Branch { DstBlock "Display15" DstPort 1 } } Line { SrcBlock "From13" SrcPort 1 DstBlock "position" DstPort 6 } Line { SrcBlock "From12" SrcPort 1 DstBlock "position" DstPort 5 } Line { SrcBlock "From15" SrcPort 1 DstBlock "position" DstPort 8 } Line { SrcBlock "From14" SrcPort 1 DstBlock "position" DstPort 7 } Line { SrcBlock "position" SrcPort 3 Points [30, 0] Branch { DstBlock "xmult_pos" DstPort 1 } Branch { DstBlock "Display16" DstPort 1 } } Line { SrcBlock "From17" SrcPort 1 DstBlock "position" DstPort 10 } Line { SrcBlock "From16" SrcPort 1 DstBlock "position" DstPort 9 } Line { SrcBlock "From19" SrcPort 1 DstBlock "position" DstPort 12 } Line { SrcBlock "From18" SrcPort 1 DstBlock "position" DstPort 11 } Line { SrcBlock "position" SrcPort 4 Points [30, 0] Branch { DstBlock "xmult_pos1" DstPort 1 } Branch { DstBlock "Display17" DstPort 1 } } } } Block { BlockType SubSystem Name "convert" SID "278" Ports [4, 4] Position [455, 227, 505, 328] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Wpos" MaskStyleString "edit" MaskVariables "Wpos=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "8" System { Name "convert" Location [716, 142, 921, 450] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "279" Position [25, 28, 55, 42] IconDisplay "Port number" } Block { BlockType Inport Name "In2" SID "281" Position [25, 78, 55, 92] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In3" SID "283" Position [25, 218, 55, 232] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "In4" SID "285" Position [25, 268, 55, 282] Port "4" IconDisplay "Port number" } Block { BlockType DataTypeConversion Name "Data Type Conversion" SID "272" Position [80, 27, 125, 43] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion1" SID "273" Position [80, 77, 125, 93] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion2" SID "274" Position [80, 217, 125, 233] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion3" SID "275" Position [80, 267, 125, 283] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "Out1" SID "280" Position [150, 28, 180, 42] IconDisplay "Port number" } Block { BlockType Outport Name "Out2" SID "282" Position [150, 78, 180, 92] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out3" SID "284" Position [150, 218, 180, 232] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Out4" SID "286" Position [150, 268, 180, 282] Port "4" IconDisplay "Port number" } Line { SrcBlock "In1" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "In2" SrcPort 1 DstBlock "Data Type Conversion1" DstPort 1 } Line { SrcBlock "Data Type Conversion1" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "In3" SrcPort 1 DstBlock "Data Type Conversion2" DstPort 1 } Line { SrcBlock "Data Type Conversion2" SrcPort 1 DstBlock "Out3" DstPort 1 } Line { SrcBlock "In4" SrcPort 1 DstBlock "Data Type Conversion3" DstPort 1 } Line { SrcBlock "Data Type Conversion3" SrcPort 1 DstBlock "Out4" DstPort 1 } } } Block { BlockType SubSystem Name "convert1" SID "773" Ports [4, 4] Position [355, 472, 410, 588] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskPromptString "Wpos" MaskStyleString "edit" MaskVariables "Wpos=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "16" System { Name "convert1" Location [716, 142, 921, 450] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In1" SID "774" Position [25, 28, 55, 42] IconDisplay "Port number" } Block { BlockType Inport Name "In2" SID "775" Position [25, 78, 55, 92] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In3" SID "776" Position [25, 218, 55, 232] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "In4" SID "777" Position [25, 268, 55, 282] Port "4" IconDisplay "Port number" } Block { BlockType DataTypeConversion Name "Data Type Conversion" SID "778" Position [80, 27, 125, 43] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion1" SID "779" Position [80, 77, 125, 93] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion2" SID "780" Position [80, 217, 125, 233] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion3" SID "781" Position [80, 267, 125, 283] ZOrder -7 ShowName off OutDataTypeStr "fixdt(0,Wpos,0)" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "Out1" SID "782" Position [150, 28, 180, 42] IconDisplay "Port number" } Block { BlockType Outport Name "Out2" SID "783" Position [150, 78, 180, 92] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out3" SID "784" Position [150, 218, 180, 232] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Out4" SID "785" Position [150, 268, 180, 282] Port "4" IconDisplay "Port number" } Line { SrcBlock "Data Type Conversion3" SrcPort 1 DstBlock "Out4" DstPort 1 } Line { SrcBlock "In4" SrcPort 1 DstBlock "Data Type Conversion3" DstPort 1 } Line { SrcBlock "Data Type Conversion2" SrcPort 1 DstBlock "Out3" DstPort 1 } Line { SrcBlock "In3" SrcPort 1 DstBlock "Data Type Conversion2" DstPort 1 } Line { SrcBlock "Data Type Conversion1" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "In2" SrcPort 1 DstBlock "Data Type Conversion1" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } } } Block { BlockType SubSystem Name "mac" SID "4" Ports [2, 1] Position [630, 23, 720, 147] ZOrder -16 slprops.hdlblkprops { $PropName "HDLData" $ObjectID 95 archSelection "Module" Array { Type "Cell" Dimension 6 Cell "DistributedPipelining" Cell "on" Cell "InputPipeline" Cell [1.0] Cell "OutputPipeline" Cell [1.0] PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH" MaskDescription "Please, print the parameter n for\nbasis (2^n-1, 2^n, 2^n+1)" MaskPromptString "n" MaskStyleString "edit" MaskVariables "WIDTH=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "9" System { Name "mac" Location [579, 89, 1780, 1030] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "a" SID "102" Position [340, 433, 370, 447] ZOrder 33 IconDisplay "Port number" } Block { BlockType Inport Name "b" SID "7" Position [340, 568, 370, 582] ZOrder -1 Port "2" IconDisplay "Port number" } Block { BlockType Delay Name "Delay3" SID "148" Ports [1, 1] Position [1080, 423, 1115, 457] ZOrder 36 InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay4" SID "149" Ports [1, 1] Position [1080, 458, 1115, 492] ZOrder 37 InputPortMap "u0" DelayLength "1" } Block { BlockType Delay Name "Delay5" SID "150" Ports [1, 1] Position [1080, 493, 1115, 527] ZOrder 38 InputPortMap "u0" DelayLength "1" } Block { BlockType Reference Name "add2nmp" SID "99" Ports [6, 3] Position [900, 402, 980, 563] ZOrder 30 LibraryVersion "1.40" SourceBlock "resedue_lib/add2nmp" SourceType "WIDTH of input value" WIDTH "WIDTH" } Block { BlockType Reference Name "forward2nmp" SID "79" Ports [1, 3] Position [400, 524, 460, 626] ZOrder 10 LibraryVersion "1.40" SourceBlock "resedue_lib/forward2nmp" SourceType "WIDTH of input value" WIDTH "WIDTH" } Block { BlockType Reference Name "forward2nmp4" SID "101" Ports [1, 3] Position [410, 389, 470, 491] ZOrder 32 LibraryVersion "1.40" SourceBlock "resedue_lib/forward2nmp" SourceType "WIDTH of input value" WIDTH "WIDTH" } Block { BlockType Reference Name "mul2nmp" SID "100" Ports [6, 3] Position [550, 432, 630, 593] ZOrder 31 LibraryVersion "1.40" SourceBlock "resedue_lib/mul2nmp" SourceType "WIDTH of input value" WIDTH "WIDTH" } Block { BlockType Reference Name "reverse2nmp" SID "138" Ports [3, 1] Position [1195, 425, 1260, 525] ZOrder 69 LibraryVersion "1.40" SourceBlock "resedue_lib/reverse2nmp" SourceType "WIDTH of input value" WIDTH "WIDTH" } Block { BlockType Outport Name "y" SID "23" Position [1310, 468, 1340, 482] ZOrder -17 IconDisplay "Port number" } Line { SrcBlock "b" SrcPort 1 DstBlock "forward2nmp" DstPort 1 } Line { SrcBlock "a" SrcPort 1 DstBlock "forward2nmp4" DstPort 1 } Line { SrcBlock "forward2nmp4" SrcPort 3 Points [27, 0; 0, 25] DstBlock "mul2nmp" DstPort 3 } Line { SrcBlock "forward2nmp4" SrcPort 2 Points [41, 0; 0, 35] DstBlock "mul2nmp" DstPort 2 } Line { SrcBlock "forward2nmp4" SrcPort 1 Points [55, 0; 0, 45] DstBlock "mul2nmp" DstPort 1 } Line { SrcBlock "forward2nmp" SrcPort 2 Points [35, 0; 0, -25] DstBlock "mul2nmp" DstPort 5 } Line { SrcBlock "forward2nmp" SrcPort 3 Points [50, 0; 0, -35] DstBlock "mul2nmp" DstPort 6 } Line { SrcBlock "mul2nmp" SrcPort 1 Points [32, 0; 0, 35] DstBlock "add2nmp" DstPort 4 } Line { SrcBlock "mul2nmp" SrcPort 2 Points [14, 0; 0, 5] DstBlock "add2nmp" DstPort 5 } Line { SrcBlock "mul2nmp" SrcPort 3 Points [5, 0; 0, -25] DstBlock "add2nmp" DstPort 6 } Line { SrcBlock "reverse2nmp" SrcPort 1 DstBlock "y" DstPort 1 } Line { SrcBlock "add2nmp" SrcPort 1 Points [40, 0; 0, 10] DstBlock "Delay3" DstPort 1 } Line { SrcBlock "add2nmp" SrcPort 2 Points [40, 0; 0, -10] DstBlock "Delay4" DstPort 1 } Line { SrcBlock "add2nmp" SrcPort 3 Points [40, 0; 0, -30] DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [20, 0] Branch { DstBlock "reverse2nmp" DstPort 1 } Branch { Points [0, -55; -255, 0] DstBlock "add2nmp" DstPort 1 } } Line { SrcBlock "Delay4" SrcPort 1 Points [30, 0] Branch { DstBlock "reverse2nmp" DstPort 2 } Branch { Points [0, -110; -275, 0; 0, 80] DstBlock "add2nmp" DstPort 2 } } Line { SrcBlock "Delay5" SrcPort 1 Points [40, 0] Branch { DstBlock "reverse2nmp" DstPort 3 } Branch { Points [0, -160; -295, 0; 0, 120] DstBlock "add2nmp" DstPort 3 } } Line { SrcBlock "forward2nmp" SrcPort 1 Points [35, 0; 0, -15] DstBlock "mul2nmp" DstPort 4 } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "mac" DstPort 2 } Line { SrcBlock "mac" SrcPort 1 Points [130, 0] DstBlock "Scope" DstPort 1 } Line { SrcBlock "Conversion" SrcPort 1 DstBlock "mac" DstPort 1 } Line { SrcBlock "Step" SrcPort 1 DstBlock "Switch" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 Points [25, 0; 0, 25] DstBlock "Switch" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 Points [25, 0; 0, -30] DstBlock "Switch" DstPort 3 } Line { SrcBlock "Switch" SrcPort 1 Points [20, 0; 0, -5] DstBlock "Conversion" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "convert" DstPort 1 } Line { SrcBlock "convert" SrcPort 1 Points [25, 0] DstBlock "complex" DstPort 1 } Line { SrcBlock "convert" SrcPort 2 Points [25, 0] DstBlock "complex" DstPort 2 } Line { SrcBlock "convert" SrcPort 3 Points [25, 0] DstBlock "complex" DstPort 3 } Line { SrcBlock "convert" SrcPort 4 Points [25, 0] DstBlock "complex" DstPort 4 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "convert" DstPort 4 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "convert" DstPort 3 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "convert" DstPort 2 } Line { SrcBlock "complex" SrcPort 1 Points [95, 0] DstBlock "Display10" DstPort 1 } Line { SrcBlock "complex" SrcPort 2 Points [0, -30] DstBlock "Display1" DstPort 1 } Line { SrcBlock "complex" SrcPort 3 Points [0, -25] DstBlock "Display2" DstPort 1 } Line { SrcBlock "complex" SrcPort 4 Points [0, -20] DstBlock "Display3" DstPort 1 } Line { SrcBlock "FIR_complex" SrcPort 1 Points [30, 0; 0, -35] DstBlock "Scope1" DstPort 1 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "convert1" DstPort 1 } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "convert1" DstPort 2 } Line { SrcBlock "Constant10" SrcPort 1 DstBlock "convert1" DstPort 3 } Line { SrcBlock "Constant11" SrcPort 1 DstBlock "convert1" DstPort 4 } Line { SrcBlock "convert1" SrcPort 1 Points [120, 0] DstBlock "FIR_complex" DstPort 1 } Line { SrcBlock "convert1" SrcPort 2 Points [120, 0] DstBlock "FIR_complex" DstPort 2 } } } # Finite State Machines # # Stateflow Version 7.6 (R2011b) dated Jan 25 2012, 13:50:40 # # Stateflow { machine { id 1 name "modul_convolution" created "05-Jun-2014 10:45:39" isLibrary 0 firstTarget 97 sfVersion 76014001.00040001 } chart { id 2 name "complex/forwardReIm/forward" windowPosition [570.75 8.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 3 0 0] firstTransition 5 firstJunction 4 viewObj 2 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 21 decomposition CLUSTER_CHART type EML_CHART firstData 6 chartFileNumber 1 disableImplicitCasting 1 eml { name "fcn" } } state { id 3 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 2 treeNode [2 0 0 0] superState SUBCHART subviewer 2 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [v, v_] = fcn(x,y,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n qm_fix = fi(Qm,0," "Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n\n v = fi(mod(x+qp_fix*y,p_fix),0,Wmod,0);\n v_ = fi(mod(x+qm_fix*y" ",p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 4 position [23.5747 49.5747 7] chart 2 linkNode [2 0 0] subviewer 2 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 5 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 4 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 2 linkNode [2 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 2 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 6 ssIdNumber 4 name "x" linkNode [2 0 7] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "Wpos" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,Wpos,0)" } data { id 7 ssIdNumber 6 name "v" linkNode [2 6 8] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 8 ssIdNumber 11 name "y" description "xcdfghb" linkNode [2 7 9] scope INPUT_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_UINT8_TYPE wordLength "Wpos" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wpos,0)" } data { id 9 ssIdNumber 15 name "v_" linkNode [2 8 10] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 10 ssIdNumber 17 name "Wmod" linkNode [2 9 11] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 11 ssIdNumber 19 name "P" linkNode [2 10 12] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 12 ssIdNumber 20 name "Qp" linkNode [2 11 13] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 13 ssIdNumber 21 name "Qm" linkNode [2 12 0] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 14 name "complex/forwardReIm/forward" machine 1 chart 2 } chart { id 15 name "complex/reverseReIm/reverse" windowPosition [585.75 -6.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 16 0 0] firstTransition 18 firstJunction 17 viewObj 15 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 23 decomposition CLUSTER_CHART type EML_CHART firstData 19 chartFileNumber 2 disableImplicitCasting 1 eml { name "fcn" } } state { id 16 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 15 treeNode [15 0 0 0] superState SUBCHART subviewer 15 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [Re, Im] = fcn(v,v_,Wmod,P,P2,P2Q)\n\n% qp_fix = fi(Qp,0,Wmod,0);\n% qm_fix = fi(" "Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n two = fi(2,0,Wmod,0);\n\n Re = fi(mod(mod((v+v_),p_fix) * P2 " ",p_fix),0,Wmod,0);\n Im = fi(mod(mod((p_fix+v-v_),p_fix) * P2Q, p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 17 position [23.5747 49.5747 7] chart 15 linkNode [15 0 0] subviewer 15 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 18 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 17 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 15 linkNode [15 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 15 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 19 ssIdNumber 6 name "v" linkNode [15 0 20] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 20 ssIdNumber 15 name "v_" linkNode [15 19 21] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 21 ssIdNumber 17 name "Wmod" linkNode [15 20 22] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 22 ssIdNumber 19 name "P" linkNode [15 21 23] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 23 ssIdNumber 20 name "P2" linkNode [15 22 24] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 24 ssIdNumber 21 name "P2Q" linkNode [15 23 25] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 25 ssIdNumber 22 name "Re" linkNode [15 24 26] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 26 ssIdNumber 23 name "Im" linkNode [15 25 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 27 name "complex/reverseReIm/reverse" machine 1 chart 15 } chart { id 28 name "complex/sumReIm/sum" windowPosition [600.75 -21.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 29 0 0] firstTransition 31 firstJunction 30 viewObj 28 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 25 decomposition CLUSTER_CHART type EML_CHART firstData 32 chartFileNumber 3 disableImplicitCasting 1 eml { name "fcn" } } state { id 29 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 28 treeNode [28 0 0 0] superState SUBCHART subviewer 28 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [sumv, sumv_] = fcn(v1,v1_,v2,v2_,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n q" "m_fix = fi(Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n \n if( (v1+v2) >= p_fix)\n sumv = fi( v1+v2" " - p_fix,0,Wmod,0);\n else \n sumv = fi( v1+v2,0,Wmod,0);\n end\n \n if( (v1_+v2_) >= p_fix)\n" " sumv_ = fi( v1_+v2_ - p_fix,0,Wmod,0);\n else \n sumv_ = fi( v1_+v2_,0,Wmod,0);\n end\n " "\n %sumv_ = fi(mod((v1_+v2_),p_fix),0,Wmod,0);\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 30 position [23.5747 49.5747 7] chart 28 linkNode [28 0 0] subviewer 28 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 31 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 30 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 28 linkNode [28 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 28 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 32 ssIdNumber 6 name "v1" linkNode [28 0 33] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 33 ssIdNumber 15 name "v1_" linkNode [28 32 34] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 34 ssIdNumber 24 name "v2" linkNode [28 33 35] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 35 ssIdNumber 25 name "v2_" linkNode [28 34 36] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 36 ssIdNumber 17 name "Wmod" linkNode [28 35 37] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 37 ssIdNumber 19 name "P" linkNode [28 36 38] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 38 ssIdNumber 20 name "Qp" linkNode [28 37 39] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 39 ssIdNumber 21 name "Qm" linkNode [28 38 40] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 40 ssIdNumber 22 name "sumv" linkNode [28 39 41] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 41 ssIdNumber 23 name "sumv_" linkNode [28 40 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 42 name "complex/sumReIm/sum" machine 1 chart 28 } chart { id 43 name "complex/forwardReIm1/forward" windowPosition [585.75 -6.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 44 0 0] firstTransition 46 firstJunction 45 viewObj 43 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 21 decomposition CLUSTER_CHART type EML_CHART firstData 47 chartFileNumber 4 disableImplicitCasting 1 eml { name "fcn" } } state { id 44 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 43 treeNode [43 0 0 0] superState SUBCHART subviewer 43 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [v, v_] = fcn(x,y,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n qm_fix = fi(Qm,0," "Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n\n v = fi(mod(x+qp_fix*y,p_fix),0,Wmod,0);\n v_ = fi(mod(x+qm_fix*y" ",p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 45 position [23.5747 49.5747 7] chart 43 linkNode [43 0 0] subviewer 43 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 46 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 45 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 43 linkNode [43 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 43 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 47 ssIdNumber 4 name "x" linkNode [43 0 48] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "Wpos" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,Wpos,0)" } data { id 48 ssIdNumber 6 name "v" linkNode [43 47 49] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 49 ssIdNumber 11 name "y" description "xcdfghb" linkNode [43 48 50] scope INPUT_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_UINT8_TYPE wordLength "Wpos" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wpos,0)" } data { id 50 ssIdNumber 15 name "v_" linkNode [43 49 51] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 51 ssIdNumber 17 name "Wmod" linkNode [43 50 52] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 52 ssIdNumber 19 name "P" linkNode [43 51 53] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 53 ssIdNumber 20 name "Qp" linkNode [43 52 54] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 54 ssIdNumber 21 name "Qm" linkNode [43 53 0] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 55 name "complex/forwardReIm1/forward" machine 1 chart 43 } chart { id 56 name "complex/multReIm/mult" windowPosition [615.75 -36.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 57 0 0] firstTransition 59 firstJunction 58 viewObj 56 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 25 decomposition CLUSTER_CHART type EML_CHART firstData 60 chartFileNumber 5 disableImplicitCasting 1 eml { name "fcn" } } state { id 57 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 56 treeNode [56 0 0 0] superState SUBCHART subviewer 56 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [sumv, sumv_] = fcn(v1,v1_,v2,v2_,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n q" "m_fix = fi(Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n\n sumv = fi(mod((v1*v2),p_fix),0,Wmod,0);\n sumv_ " "= fi(mod((v1_*v2_),p_fix),0,Wmod,0);\n\n% sumv = fi(res((v1*v2),P,Wmod),0,Wmod,0);\n% sumv_ = fi(res((v1_*" "v2_),P,Wmod),0,Wmod,0);\n \nend\n\nfunction z = res(a,module,Wmod)\n for k = 1:module\n if(a > modu" "le)\n a = fi(a - module,0,Wmod*2,0);\n end\n end\n z = a;\nend\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 58 position [23.5747 49.5747 7] chart 56 linkNode [56 0 0] subviewer 56 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 59 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 58 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 56 linkNode [56 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 56 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 60 ssIdNumber 6 name "v1" linkNode [56 0 61] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 61 ssIdNumber 15 name "v1_" linkNode [56 60 62] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 62 ssIdNumber 24 name "v2" linkNode [56 61 63] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 63 ssIdNumber 25 name "v2_" linkNode [56 62 64] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 64 ssIdNumber 17 name "Wmod" linkNode [56 63 65] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 65 ssIdNumber 19 name "P" linkNode [56 64 66] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 66 ssIdNumber 20 name "Qp" linkNode [56 65 67] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 67 ssIdNumber 21 name "Qm" linkNode [56 66 68] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 68 ssIdNumber 22 name "sumv" linkNode [56 67 69] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 69 ssIdNumber 23 name "sumv_" linkNode [56 68 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 70 name "complex/multReIm/mult" machine 1 chart 56 } chart { id 71 name "complex/reverseReIm1/reverse" windowPosition [600.75 -21.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 72 0 0] firstTransition 74 firstJunction 73 viewObj 71 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 23 decomposition CLUSTER_CHART type EML_CHART firstData 75 chartFileNumber 6 disableImplicitCasting 1 eml { name "fcn" } } state { id 72 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 71 treeNode [71 0 0 0] superState SUBCHART subviewer 71 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [Re, Im] = fcn(v,v_,Wmod,P,P2,P2Q)\n\n% qp_fix = fi(Qp,0,Wmod,0);\n% qm_fix = fi(" "Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n two = fi(2,0,Wmod,0);\n\n Re = fi(mod(mod((v+v_),p_fix) * P2 " ",p_fix),0,Wmod,0);\n Im = fi(mod(mod((p_fix+v-v_),p_fix) * P2Q, p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 73 position [23.5747 49.5747 7] chart 71 linkNode [71 0 0] subviewer 71 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 74 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 73 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 71 linkNode [71 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 71 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 75 ssIdNumber 6 name "v" linkNode [71 0 76] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 76 ssIdNumber 15 name "v_" linkNode [71 75 77] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 77 ssIdNumber 17 name "Wmod" linkNode [71 76 78] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 78 ssIdNumber 19 name "P" linkNode [71 77 79] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 79 ssIdNumber 20 name "P2" linkNode [71 78 80] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 80 ssIdNumber 21 name "P2Q" linkNode [71 79 81] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 81 ssIdNumber 22 name "Re" linkNode [71 80 82] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 82 ssIdNumber 23 name "Im" linkNode [71 81 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 83 name "complex/reverseReIm1/reverse" machine 1 chart 71 } chart { id 84 name "complex/reverseReIm2/reverse" windowPosition [615.75 -36.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 85 0 0] firstTransition 87 firstJunction 86 viewObj 84 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 23 decomposition CLUSTER_CHART type EML_CHART firstData 88 chartFileNumber 7 disableImplicitCasting 1 eml { name "fcn" } } state { id 85 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 84 treeNode [84 0 0 0] superState SUBCHART subviewer 84 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [Re, Im] = fcn(v,v_,Wmod,P,P2,P2Q)\n\n% qp_fix = fi(Qp,0,Wmod,0);\n% qm_fix = fi(" "Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n two = fi(2,0,Wmod,0);\n\n Re = fi(mod(mod((v+v_),p_fix) * P2 " ",p_fix),0,Wmod,0);\n Im = fi(mod(mod((p_fix+v-v_),p_fix) * P2Q, p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 86 position [23.5747 49.5747 7] chart 84 linkNode [84 0 0] subviewer 84 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 87 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 86 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 84 linkNode [84 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 84 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 88 ssIdNumber 6 name "v" linkNode [84 0 89] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 89 ssIdNumber 15 name "v_" linkNode [84 88 90] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 90 ssIdNumber 17 name "Wmod" linkNode [84 89 91] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 91 ssIdNumber 19 name "P" linkNode [84 90 92] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 92 ssIdNumber 20 name "P2" linkNode [84 91 93] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 93 ssIdNumber 21 name "P2Q" linkNode [84 92 94] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 94 ssIdNumber 22 name "Re" linkNode [84 93 95] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 95 ssIdNumber 23 name "Im" linkNode [84 94 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 96 name "complex/reverseReIm2/reverse" machine 1 chart 84 } target { id 97 name "sfun" description "Default Simulink S-Function Target." machine 1 linkNode [1 0 98] } target { id 98 name "slhdlc" codeFlags " comments=1 emitdescriptions=1" machine 1 linkNode [1 97 0] } }