Library { Name "resedue_lib" Version 7.9 MdlSubVersion 0 SavedCharacterEncoding "UTF-8" LibraryType "BlockLibrary" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off FPTRunName "Run 1" MaxMDLFileLineLength 120 InitFcn "%% DSPBuilder Start\nalt_dspbuilder_update_model(bdroot)\n%% DSPBuilder End\n" Created "Wed Jun 04 17:51:55 2014" Creator "root" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "root" ModifiedDateFormat "%" LastModifiedDate "Thu Oct 30 16:27:32 2014" RTWModifiedTimeStamp 336571462 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "all" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowDesignRanges off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" RecordCoverage off CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.12.0" Array { Type "Handle" Dimension 9 Simulink.SolverCC { $ObjectID 2 Version "1.12.0" StartTime "0.0" StopTime "10.0" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "Auto" EnableConcurrentExecution off ConcurrentTasks off Solver "ode45" SolverName "ode45" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.12.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.12.0" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off UseFloatMulNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off ParallelExecutionInRapidAccelerator on } Simulink.DebuggingCC { $ObjectID 5 Version "1.12.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Enable All" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" FrameProcessingCompatibilityMsg "warning" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.12.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.12.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 8 Version "1.12.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.12.0" Array { Type "Cell" Dimension 9 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateWebview" Cell "GenerateCodeMetricsReport" Cell "GenerateCodeReplacementReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateWebview off GenerateCodeMetricsReport off GenerateCodeReplacementReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.12.0" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.12.0" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" CodeReplacementLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on ConcurrentExecutionCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns on CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off GRTInterface off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } hdlcoderui.hdlcc { $ObjectID 12 Version "1.12.0" Description "HDL Coder custom configuration component" Name "HDL Coder" Array { Type "Cell" Dimension 1 Cell "" PropName "HDLConfigFile" } HDLCActiveTab "0" } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 520, 225, 1400, 855 ] } PropName "ConfigurationSets" } ExplicitPartitioning off BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Demux Outputs "4" DisplayOption "none" BusSelectionMode off } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType S-Function FunctionName "system" SFunctionModules "''" PortCounts "[]" SFunctionDeploymentMode off } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" SFBlockType "NONE" Variant off GeneratePreprocessorConditionals off } Block { BlockType Terminator } } System { Name "resedue_lib" Location [4, 49, 884, 929] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "540" Block { BlockType SubSystem Name "MULT_LUT" SID "348" Ports [] Position [328, 442, 455, 525] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MULT_LUT" Location [652, 152, 1306, 1017] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType SubSystem Name "mult_101lut" SID "349" Ports [2, 1] Position [350, 319, 395, 361] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 13 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_101lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "350" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "351" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "352" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_101_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_101.vo" src_file "src/multiplication_mod_101.v;" TopLevelName "multiplication_mod_101" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "353" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F101lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "354" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F101lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "355" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F101lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "356" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_109lut" SID "357" Ports [2, 1] Position [350, 384, 395, 426] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 14 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_109lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "358" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "359" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "360" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_109_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_109.vo" src_file "src/multiplication_mod_109.v;" TopLevelName "multiplication_mod_109" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "361" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F109lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "362" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F109lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "363" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F109lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "364" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_113lut" SID "365" Ports [2, 1] Position [350, 444, 395, 486] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 15 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_113lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "366" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "367" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "368" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_113_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_modul_basic_import/multiplication_mod_113.vo" src_file "src/multiplication_mod_113.v;" TopLevelName "multiplication_mod_113" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "369" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F113lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "370" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F113lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "371" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F113lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "372" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_137lut" SID "373" Ports [2, 1] Position [425, 54, 470, 96] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 16 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_137lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "374" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "375" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "376" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_137_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_137.vo" src_file "src/multiplication_mod_137.v;" TopLevelName "multiplication_mod_137" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "377" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F137lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "378" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F137lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "379" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F137lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "380" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_13lut" SID "381" Ports [2, 1] Position [125, 54, 170, 96] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 17 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_13lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "382" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "383" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "384" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_13_import" inNames "inp1 inp2 " inBwls "4 4 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "4 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_13.vo" src_file "src/multiplication_mod_13.v;" TopLevelName "multiplication_mod_13" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "385" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F13lut_Input.salt" BusType "Unsigned Integer" bwl "4" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "386" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F13lut_Input1.salt" BusType "Unsigned Integer" bwl "4" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "387" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F13lut_Output.capture" BusType "Unsigned Integer" bwl "4" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "388" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_149lut" SID "389" Ports [2, 1] Position [425, 124, 470, 166] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 18 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_149lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "390" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "391" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "392" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_149_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_149.vo" src_file "src/multiplication_mod_149.v;" TopLevelName "multiplication_mod_149" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "393" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F149lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "394" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F149lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "395" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F149lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "396" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_157lut" SID "397" Ports [2, 1] Position [425, 189, 470, 231] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 19 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_157lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "398" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "399" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "400" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_157_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_157.vo" src_file "src/multiplication_mod_157.v;" TopLevelName "multiplication_mod_157" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "401" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F157lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "402" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F157lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "403" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F157lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "404" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_173lut" SID "405" Ports [2, 1] Position [425, 254, 470, 296] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 20 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_173lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "406" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "407" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "408" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_173_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_173.vo" src_file "src/multiplication_mod_173.v;" TopLevelName "multiplication_mod_173" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "409" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F173lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "410" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F173lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "411" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F173lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "412" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_17lut" SID "413" Ports [2, 1] Position [200, 54, 245, 96] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 21 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_17lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "414" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "415" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "416" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_17_import" inNames "inp1 inp2 " inBwls "5 5 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "5 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_17.vo" src_file "src/multiplication_mod_17.v;" TopLevelName "multiplication_mod_17" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "417" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F17lut_Input.salt" BusType "Unsigned Integer" bwl "5" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "418" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F17lut_Input1.salt" BusType "Unsigned Integer" bwl "5" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "419" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F17lut_Output.capture" BusType "Unsigned Integer" bwl "5" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "420" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_181lut" SID "421" Ports [2, 1] Position [425, 319, 470, 361] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 22 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_181lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "422" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "423" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "424" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_181_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_181.vo" src_file "src/multiplication_mod_181.v;" TopLevelName "multiplication_mod_181" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "425" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F181lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "426" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F181lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "427" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F181lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "428" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_193lut" SID "429" Ports [2, 1] Position [425, 384, 470, 426] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 23 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_193lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "430" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "431" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "432" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_193_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_193.vo" src_file "src/multiplication_mod_193.v;" TopLevelName "multiplication_mod_193" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "433" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F193lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "434" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F193lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "435" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F193lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "436" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_197lut" SID "437" Ports [2, 1] Position [425, 444, 470, 486] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 24 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_197lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "438" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "439" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "440" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_197_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_197.vo" src_file "src/multiplication_mod_197.v;" TopLevelName "multiplication_mod_197" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "441" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F197lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "442" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F197lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "443" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F197lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "444" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_229lut" SID "445" Ports [2, 1] Position [425, 504, 470, 546] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 25 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_229lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "446" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "447" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "448" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_229_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_229.vo" src_file "src/multiplication_mod_229.v;" TopLevelName "multiplication_mod_229" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "449" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F229lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "450" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F229lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "451" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F229lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "452" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_233lut" SID "453" Ports [2, 1] Position [425, 569, 470, 611] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 26 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_233lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "454" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "455" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "456" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_233_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_233.vo" src_file "src/multiplication_mod_233.v;" TopLevelName "multiplication_mod_233" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "457" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F233lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "458" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F233lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "459" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F233lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "460" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_241lut" SID "461" Ports [2, 1] Position [425, 629, 470, 671] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 27 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_241lut" Location [857, 129, 1423, 469] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "462" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "463" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "464" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_241_import" inNames "inp1 inp2 " inBwls "8 8 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "8 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_241.vo" src_file "src/multiplication_mod_241.v;" TopLevelName "multiplication_mod_241" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "465" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F241lut_Input.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "466" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F241lut_Input1.salt" BusType "Unsigned Integer" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "467" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F241lut_Output.capture" BusType "Unsigned Integer" bwl "8" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "468" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_29lut" SID "469" Ports [2, 1] Position [200, 114, 245, 156] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 28 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_29lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "470" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "471" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "472" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_29_import" inNames "inp1 inp2 " inBwls "5 5 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "5 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_29.vo" src_file "src/multiplication_mod_29.v;" TopLevelName "multiplication_mod_29" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "473" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F29lut_Input.salt" BusType "Unsigned Integer" bwl "5" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "474" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F29lut_Input1.salt" BusType "Unsigned Integer" bwl "5" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "475" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F29lut_Output.capture" BusType "Unsigned Integer" bwl "5" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "476" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_37lut" SID "477" Ports [2, 1] Position [275, 54, 320, 96] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 29 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_37lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "478" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "479" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "480" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_37_import" inNames "inp1 inp2 " inBwls "6 6 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "6 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_37.vo" src_file "src/multiplication_mod_37.v;" TopLevelName "multiplication_mod_37" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "481" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F37lut_Input.salt" BusType "Unsigned Integer" bwl "6" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "482" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F37lut_Input1.salt" BusType "Unsigned Integer" bwl "6" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "483" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F37lut_Output.capture" BusType "Unsigned Integer" bwl "6" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "484" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_41lut" SID "485" Ports [2, 1] Position [275, 124, 320, 166] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 30 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_41lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "486" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "487" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "488" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_41_import" inNames "inp1 inp2 " inBwls "6 6 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "6 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_41.vo" src_file "src/multiplication_mod_41.v;" TopLevelName "multiplication_mod_41" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "489" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F41lut_Input.salt" BusType "Unsigned Integer" bwl "6" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "490" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F41lut_Input1.salt" BusType "Unsigned Integer" bwl "6" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "491" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F41lut_Output.capture" BusType "Unsigned Integer" bwl "6" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "492" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_53lut" SID "493" Ports [2, 1] Position [275, 189, 320, 231] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 31 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_53lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "494" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "495" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "496" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_53_import" inNames "inp1 inp2 " inBwls "6 6 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "6 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_53.vo" src_file "src/multiplication_mod_53.v;" TopLevelName "multiplication_mod_53" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "497" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F53lut_Input.salt" BusType "Unsigned Integer" bwl "6" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "498" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F53lut_Input1.salt" BusType "Unsigned Integer" bwl "6" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "499" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F53lut_Output.capture" BusType "Unsigned Integer" bwl "6" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "500" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_5lut" SID "501" Ports [2, 1] Position [45, 54, 90, 96] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 32 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_5lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "502" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "503" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "504" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_5_import" inNames "inp1 inp2 " inBwls "3 3 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "3 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_5.vo" src_file "src/multiplication_mod_5.v;" TopLevelName "multiplication_mod_5" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "505" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F5lut_Input.salt" BusType "Unsigned Integer" bwl "3" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "506" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F5lut_Input1.salt" BusType "Unsigned Integer" bwl "3" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "507" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F5lut_Output.capture" BusType "Unsigned Integer" bwl "3" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "508" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_61lut" SID "509" Ports [2, 1] Position [350, 54, 395, 96] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 33 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_61" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_61lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "510" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "511" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "512" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_61_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_61.vo" src_file "src/multiplication_mod_61.v;" TopLevelName "multiplication_mod_61" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "513" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F61lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "514" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F61lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "515" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F61lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "516" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_73lut" SID "517" Ports [2, 1] Position [350, 124, 395, 166] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 34 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_73" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_73lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "518" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "519" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "520" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_73_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_modul_basic_import/multiplication_mod_73.vo" src_file "src/multiplication_mod_73.v;" TopLevelName "multiplication_mod_73" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "521" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F73lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "522" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F73lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "523" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F73lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "524" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_89lut" SID "525" Ports [2, 1] Position [350, 189, 395, 231] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 35 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_89" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_89lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "526" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "527" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "528" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_89_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_modul_basic_import/multiplication_mod_89.vo" src_file "src/multiplication_mod_89.v;" TopLevelName "multiplication_mod_89" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "529" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F89lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "530" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F89lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "531" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F89lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "532" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_97lut" SID "533" Ports [2, 1] Position [350, 254, 395, 296] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 36 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_97lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "534" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "535" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "536" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_97_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_97.vo" src_file "src/multiplication_mod_97.v;" TopLevelName "multiplication_mod_97" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "537" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F97lut_Input.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "538" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F97lut_Input1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "539" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_MULT%5FLUT_" "mult%5F97lut_Output.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "540" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } } } Block { BlockType SubSystem Name "add2nmp" SID "55" Ports [6, 3] Position [20, 157, 100, 318] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "n" MaskStyleString "edit" MaskVariables "WIDTH=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "WIDTH" System { Name "add2nmp" Location [957, 121, 1637, 761] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In2nmA" SID "56" Position [35, 128, 65, 142] IconDisplay "Port number" } Block { BlockType Inport Name "In2nA" SID "57" Position [35, 228, 65, 242] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In2npA" SID "58" Position [35, 328, 65, 342] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "In2nmB" SID "59" Position [35, 158, 65, 172] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "In2nB" SID "60" Position [35, 258, 65, 272] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "In2npB" SID "61" Position [35, 358, 65, 372] Port "6" IconDisplay "Port number" } Block { BlockType SubSystem Name "add2n" SID "62" Ports [2, 1] Position [230, 222, 300, 278] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "add2n" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "48" Block { BlockType Inport Name "A" SID "62::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "62::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "62::34" Ports [1, 1] Position [270, 160, 320, 200] ZOrder 21 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "62::33" Tag "Stateflow S-Function resedue_lib 14" Ports [2, 2] Position [180, 100, 230, 160] ZOrder 20 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "62::36" Position [460, 171, 480, 189] ZOrder 23 } Block { BlockType Outport Name "z" SID "62::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType SubSystem Name "add2nm" SID "63" Ports [2, 1] Position [230, 122, 300, 178] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "add2nm" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "48" Block { BlockType Inport Name "A" SID "63::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "63::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "63::34" Ports [1, 1] Position [270, 160, 320, 200] ZOrder 21 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "63::33" Tag "Stateflow S-Function resedue_lib 17" Ports [2, 2] Position [180, 100, 230, 160] ZOrder 20 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "63::36" Position [460, 171, 480, 189] ZOrder 23 } Block { BlockType Outport Name "z" SID "63::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType SubSystem Name "add2np" SID "64" Ports [2, 1] Position [230, 322, 300, 378] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "add2np" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "48" Block { BlockType Inport Name "A" SID "64::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "64::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "64::34" Ports [1, 1] Position [270, 160, 320, 200] ZOrder 21 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "64::33" Tag "Stateflow S-Function resedue_lib 18" Ports [2, 2] Position [180, 100, 230, 160] ZOrder 20 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "64::36" Position [460, 171, 480, 189] ZOrder 23 } Block { BlockType Outport Name "z" SID "64::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "Out2nm" SID "65" Position [420, 143, 450, 157] IconDisplay "Port number" } Block { BlockType Outport Name "Out2n" SID "66" Position [420, 243, 450, 257] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out2np" SID "67" Position [420, 343, 450, 357] Port "3" IconDisplay "Port number" } Line { SrcBlock "In2nmB" SrcPort 1 DstBlock "add2nm" DstPort 2 } Line { SrcBlock "In2nB" SrcPort 1 DstBlock "add2n" DstPort 2 } Line { SrcBlock "In2npB" SrcPort 1 DstBlock "add2np" DstPort 2 } Line { SrcBlock "In2npA" SrcPort 1 DstBlock "add2np" DstPort 1 } Line { SrcBlock "In2nA" SrcPort 1 DstBlock "add2n" DstPort 1 } Line { SrcBlock "In2nmA" SrcPort 1 DstBlock "add2nm" DstPort 1 } Line { SrcBlock "add2nm" SrcPort 1 DstBlock "Out2nm" DstPort 1 } Line { SrcBlock "add2n" SrcPort 1 DstBlock "Out2n" DstPort 1 } Line { SrcBlock "add2np" SrcPort 1 DstBlock "Out2np" DstPort 1 } } } Block { BlockType SubSystem Name "forward2nmp" SID "7" Ports [1, 3] Position [135, 14, 195, 116] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "n" MaskStyleString "edit" MaskVariables "WIDTH=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "WIDTH" System { Name "forward2nmp" Location [241, 49, 921, 689] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "8" Position [100, 243, 130, 257] IconDisplay "Port number" } Block { BlockType SubSystem Name "forward" SID "9" Ports [1, 3] Position [230, 222, 300, 278] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "forward" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "51" Block { BlockType Inport Name "u" SID "9::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "9::19" Ports [1, 1] Position [270, 210, 320, 250] ZOrder 10 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "9::18" Tag "Stateflow S-Function resedue_lib 9" Ports [1, 4] Position [180, 106, 230, 209] ZOrder 9 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[1 4]" EnableBusSupport on Port { PortNumber 2 Name "out2nm" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "out2n" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "out2np" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "9::21" Position [460, 221, 480, 239] ZOrder 12 } Block { BlockType Outport Name "out2nm" SID "9::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Block { BlockType Outport Name "out2n" SID "9::29" Position [460, 136, 480, 154] ZOrder 16 Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "out2np" SID "9::30" Position [460, 171, 480, 189] ZOrder 17 Port "3" IconDisplay "Port number" } Line { SrcBlock "u" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { Name "out2nm" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "out2nm" DstPort 1 } Line { Name "out2n" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "out2n" DstPort 1 } Line { Name "out2np" Labels [0, 0] SrcBlock " SFunction " SrcPort 4 DstBlock "out2np" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "Out2nm" SID "10" Position [420, 143, 450, 157] IconDisplay "Port number" } Block { BlockType Outport Name "Out2n" SID "11" Position [420, 243, 450, 257] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out2np" SID "12" Position [420, 343, 450, 357] Port "3" IconDisplay "Port number" } Line { SrcBlock "forward" SrcPort 2 DstBlock "Out2n" DstPort 1 } Line { SrcBlock "forward" SrcPort 1 Points [50, 0; 0, -80] DstBlock "Out2nm" DstPort 1 } Line { SrcBlock "forward" SrcPort 3 Points [50, 0; 0, 80] DstBlock "Out2np" DstPort 1 } Line { SrcBlock "In" SrcPort 1 DstBlock "forward" DstPort 1 } } } Block { BlockType SubSystem Name "forwardReIm" SID "68" Ports [2, 2] Position [325, 97, 375, 128] LibraryVersion "1.33" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit" MaskVariables "Wmod=@1;P=@2;Qp=@3;Qm=@4;" MaskTunableValueString "on,on,on,on" MaskCallbackString "|||" MaskEnableString "on,on,on,on" MaskVisibilityString "on,on,on,on" MaskToolTipString "on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wmod|P|Qp|Qm" System { Name "forwardReIm" Location [598, 272, 1278, 912] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Re" SID "69" Position [100, 243, 130, 257] IconDisplay "Port number" } Block { BlockType Inport Name "Im" SID "70" Position [100, 288, 130, 302] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "forward" SID "71" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "forward" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "47" Block { BlockType Inport Name "x" SID "71::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "y" SID "71::40" Position [20, 136, 40, 154] ZOrder 27 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "71::2" Ports [1, 1] Position [270, 180, 320, 220] ZOrder 33 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "71::1" Tag "Stateflow S-Function resedue_lib 2" Ports [2, 3] Position [180, 100, 230, 180] ZOrder 32 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[2 3]" EnableBusSupport off Port { PortNumber 2 Name "v" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "v_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "71::4" Position [460, 191, 480, 209] ZOrder 35 } Block { BlockType Outport Name "v" SID "71::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Block { BlockType Outport Name "v_" SID "71::29" Position [460, 136, 480, 154] ZOrder 16 Port "2" IconDisplay "Port number" } Line { SrcBlock "x" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "y" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "v" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "v" DstPort 1 } Line { Name "v_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "v_" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "v" SID "72" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "v_" SID "73" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "Im" SrcPort 1 Points [40, 0; 0, -20] DstBlock "forward" DstPort 2 } Line { SrcBlock "Re" SrcPort 1 Points [80, 0] DstBlock "forward" DstPort 1 } Line { SrcBlock "forward" SrcPort 1 Points [50, 0; 0, -15] DstBlock "v" DstPort 1 } Line { SrcBlock "forward" SrcPort 2 DstBlock "v_" DstPort 1 } } } Block { BlockType SubSystem Name "mul2nmp" SID "30" Ports [6, 3] Position [150, 152, 230, 313] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 37 archSelection "Module" Array { Type "Cell" Dimension 4 Cell "InputPipeline" Cell [1.0] Cell "OutputPipeline" Cell [1.0] PropName "archImplInfo" } } TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "n" MaskStyleString "edit" MaskVariables "WIDTH=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "WIDTH" System { Name "mul2nmp" Location [691, 124, 1371, 764] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In2nmA" SID "43" Position [35, 128, 65, 142] IconDisplay "Port number" } Block { BlockType Inport Name "In2nA" SID "44" Position [35, 228, 65, 242] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In2npA" SID "45" Position [35, 328, 65, 342] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "In2nmB" SID "46" Position [35, 158, 65, 172] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "In2nB" SID "47" Position [35, 258, 65, 272] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "In2npB" SID "48" Position [35, 358, 65, 372] Port "6" IconDisplay "Port number" } Block { BlockType SubSystem Name "mul2n" SID "49" Ports [2, 1] Position [230, 222, 300, 278] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "mul2n" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "44" Block { BlockType Inport Name "A" SID "49::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "49::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "49::30" Ports [1, 1] Position [270, 160, 320, 200] ZOrder 29 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "49::29" Tag "Stateflow S-Function resedue_lib 1" Ports [2, 2] Position [180, 100, 230, 160] ZOrder 28 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "49::32" Position [460, 171, 480, 189] ZOrder 31 } Block { BlockType Outport Name "z" SID "49::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType SubSystem Name "mul2nm" SID "50" Ports [2, 1] Position [230, 122, 300, 178] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "mul2nm" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "44" Block { BlockType Inport Name "A" SID "50::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "50::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "50::30" Ports [1, 1] Position [270, 160, 320, 200] ZOrder 29 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "50::29" Tag "Stateflow S-Function resedue_lib 5" Ports [2, 2] Position [180, 100, 230, 160] ZOrder 28 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "50::32" Position [460, 171, 480, 189] ZOrder 31 } Block { BlockType Outport Name "z" SID "50::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType SubSystem Name "mul2np" SID "51" Ports [2, 1] Position [230, 322, 300, 378] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "mul2np" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "44" Block { BlockType Inport Name "A" SID "51::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "51::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "51::30" Ports [1, 1] Position [270, 160, 320, 200] ZOrder 29 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "51::29" Tag "Stateflow S-Function resedue_lib 6" Ports [2, 2] Position [180, 100, 230, 160] ZOrder 28 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "51::32" Position [460, 171, 480, 189] ZOrder 31 } Block { BlockType Outport Name "z" SID "51::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "Out2nm" SID "52" Position [420, 143, 450, 157] IconDisplay "Port number" } Block { BlockType Outport Name "Out2n" SID "53" Position [420, 243, 450, 257] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Out2np" SID "54" Position [420, 343, 450, 357] Port "3" IconDisplay "Port number" } Line { SrcBlock "In2nmB" SrcPort 1 DstBlock "mul2nm" DstPort 2 } Line { SrcBlock "In2nB" SrcPort 1 DstBlock "mul2n" DstPort 2 } Line { SrcBlock "In2npB" SrcPort 1 DstBlock "mul2np" DstPort 2 } Line { SrcBlock "In2npA" SrcPort 1 DstBlock "mul2np" DstPort 1 } Line { SrcBlock "In2nA" SrcPort 1 DstBlock "mul2n" DstPort 1 } Line { SrcBlock "In2nmA" SrcPort 1 DstBlock "mul2nm" DstPort 1 } Line { SrcBlock "mul2nm" SrcPort 1 DstBlock "Out2nm" DstPort 1 } Line { SrcBlock "mul2n" SrcPort 1 DstBlock "Out2n" DstPort 1 } Line { SrcBlock "mul2np" SrcPort 1 DstBlock "Out2np" DstPort 1 } } } Block { BlockType SubSystem Name "multReIm" SID "82" Ports [4, 2] Position [425, 166, 485, 269] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm" System { Name "multReIm" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v1" SID "83" Position [50, 218, 80, 232] IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "84" Position [50, 248, 80, 262] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "85" Position [55, 273, 85, 287] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "86" Position [55, 303, 85, 317] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "mult" SID "87" Ports [4, 2] Position [230, 232, 300, 293] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "mult" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "47" Block { BlockType Inport Name "v1" SID "87::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "87::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "87::46" Position [20, 171, 40, 189] ZOrder 33 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "87::47" Position [20, 206, 40, 224] ZOrder 34 Port "4" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "87::32" Ports [1, 1] Position [270, 280, 320, 320] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "87::31" Tag "Stateflow S-Function resedue_lib 4" Ports [4, 3] Position [180, 127, 230, 278] ZOrder 18 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[4 3]" EnableBusSupport on Port { PortNumber 2 Name "sumv" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "sumv_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "87::34" Position [460, 291, 480, 309] ZOrder 21 } Block { BlockType Outport Name "sumv" SID "87::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "87::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock "v1" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "v1_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v2" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "v2_" SrcPort 1 DstBlock " SFunction " DstPort 4 } Line { Name "sumv" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "sumv" DstPort 1 } Line { Name "sumv_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "sumv_" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "sumv" SID "88" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "89" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "mult" SrcPort 2 Points [0, -5] DstBlock "sumv_" DstPort 1 } Line { SrcBlock "v1_" SrcPort 1 DstBlock "mult" DstPort 2 } Line { SrcBlock "v1" SrcPort 1 Points [130, 0] DstBlock "mult" DstPort 1 } Line { SrcBlock "mult" SrcPort 1 Points [50, 0; 0, -20] DstBlock "sumv" DstPort 1 } Line { SrcBlock "v2" SrcPort 1 Points [60, 0; 0, -10] DstBlock "mult" DstPort 3 } Line { SrcBlock "v2_" SrcPort 1 Points [60, 0; 0, -25] DstBlock "mult" DstPort 4 } } } Block { BlockType SubSystem Name "mult_113lut" SID "140" Ports [2, 1] Position [640, 344, 685, 386] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 38 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_113" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_113lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "141" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "142" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "143" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_113_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_modul_basic_import/multiplication_mod_113.vo" src_file "src/multiplication_mod_113.v;" TopLevelName "multiplication_mod_113" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "144" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F113lut_Input" ".salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "145" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F113lut_Input" "1.salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "146" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F113lut_Outpu" "t.capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "147" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_61lut" SID "116" Ports [2, 1] Position [410, 344, 455, 386] LibraryVersion "1.39" slprops.hdlblkprops { $PropName "HDLData" $ObjectID 39 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_61" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_61lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "117" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "118" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "119" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_61_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_61.vo" src_file "src/multiplication_mod_61.v;" TopLevelName "multiplication_mod_61" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "120" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F61lut_Input." "salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "121" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F61lut_Input1" ".salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "122" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F61lut_Output" ".capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "123" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_73lut" SID "124" Ports [2, 1] Position [495, 344, 540, 386] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 40 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_73" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_73lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "125" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "126" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "127" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_73_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_modul_basic_import/multiplication_mod_73.vo" src_file "src/multiplication_mod_73.v;" TopLevelName "multiplication_mod_73" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "128" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F73lut_Input." "salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "129" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F73lut_Input1" ".salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "130" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F73lut_Output" ".capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "131" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_89lut" SID "132" Ports [2, 1] Position [570, 344, 615, 386] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 41 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_89" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_89lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "133" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "134" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "135" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_89_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_modul_basic_import/multiplication_mod_89.vo" src_file "src/multiplication_mod_89.v;" TopLevelName "multiplication_mod_89" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "136" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F89lut_Input." "salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "137" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F89lut_Input1" ".salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "138" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F89lut_Output" ".capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "139" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } } } Block { BlockType SubSystem Name "mult_97lut" SID "108" Ports [2, 1] Position [320, 344, 365, 386] slprops.hdlblkprops { $PropName "HDLData" $ObjectID 42 archSelection "BlackBox" Array { Type "Cell" Dimension 8 Cell "AddClockEnablePort" Cell "off" Cell "AddClockPort" Cell "off" Cell "AddResetPort" Cell "off" Cell "EntityName" Cell "multiplication_mod_97" PropName "archImplInfo" } } MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "mult_97lut" Location [965, 99, 1531, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "inp1" SID "109" Position [25, 43, 55, 57] IconDisplay "Port number" } Block { BlockType Inport Name "inp2" SID "110" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "HDLImport" SID "111" Ports [2, 1] Position [180, 25, 370, 125] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/HDLImport" SourceType "HDLImport AlteraBlockset" entityName "multiplication_mod_97_import" inNames "inp1 inp2 " inBwls "7 7 " inBwrs "0 0" inTypes "s s " inDelayed "0 0" outNames "out " outBwls "7 " outBwrs "0" outTypes "s " xmlmapfile "/home/ppoperechny/ProgramsFiles/altera/12.1/quartus/dsp_builder/lib/SimgenCMap.xml" vofile "DSPBuilder_resedue_lib_import/multiplication_mod_97.vo" src_file "src/multiplication_mod_97.v;" TopLevelName "multiplication_mod_97" UseQPF "0" n_input_port "2" n_output_port "1" use_systemC_model "off" is_megacore "off" use_dynamic_feedthrough_data "off" use_alphabetical_port_ordering "off" allowFloatingPointOverride off } Block { BlockType Reference Name "Input" SID "112" Ports [1, 1] Position [80, 42, 145, 58] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F97lut_Input." "salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Input1" SID "113" Ports [1, 1] Position [80, 92, 145, 108] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F97lut_Input1" ".salt" BusType "Unsigned Integer" bwl "7" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Output" SID "114" Ports [1, 1] Position [390, 67, 455, 83] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "/home/ppoperechny/things/science/IPPMRAN/matlab/resedue/tb_resedue_lib/resedue%5Flib_mult%5F97lut_Output" ".capture" BusType "Unsigned Integer" bwl "7" bwr "0" externalType "Simulink Fixed Point Type" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Outport Name "out" SID "115" Position [480, 68, 510, 82] IconDisplay "Port number" } Line { SrcBlock "HDLImport" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "Input" SrcPort 1 DstBlock "HDLImport" DstPort 1 } Line { SrcBlock "Input1" SrcPort 1 DstBlock "HDLImport" DstPort 2 } Line { SrcBlock "inp1" SrcPort 1 DstBlock "Input" DstPort 1 } Line { SrcBlock "Output" SrcPort 1 DstBlock "out" DstPort 1 } Line { SrcBlock "inp2" SrcPort 1 DstBlock "Input1" DstPort 1 } } } Block { BlockType SubSystem Name "mult_mod" SID "96" Ports [2, 1] Position [525, 200, 575, 240] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wmod|P" MaskStyleString "edit,edit" MaskVariables "Wmod=@1;P=@2;" MaskTunableValueString "on,on" MaskCallbackString "|" MaskEnableString "on,on" MaskVisibilityString "on,on" MaskToolTipString "on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wmod|P" System { Name "mult_mod" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v1" SID "97" Position [55, 243, 85, 257] IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "98" Position [55, 273, 85, 287] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "mult" SID "99" Ports [2, 1] Position [230, 234, 300, 296] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "mult" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "63" Block { BlockType Inport Name "v1" SID "99::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "99::46" Position [20, 136, 40, 154] ZOrder 33 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "99::49" Ports [1, 1] Position [270, 205, 320, 245] ZOrder 36 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "99::48" Tag "Stateflow S-Function resedue_lib 10" Ports [2, 2] Position [180, 104, 230, 206] ZOrder 35 FunctionName "sf_sfun" Parameters "P,Wmod" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "mult" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "99::51" Position [460, 216, 480, 234] ZOrder 38 } Block { BlockType Outport Name "mult" SID "99::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "mult" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "mult" DstPort 1 } Line { SrcBlock "v2" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v1" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "omult" SID "100" Position [430, 258, 460, 272] IconDisplay "Port number" } Line { SrcBlock "v1" SrcPort 1 DstBlock "mult" DstPort 1 } Line { SrcBlock "mult" SrcPort 1 DstBlock "omult" DstPort 1 } Line { SrcBlock "v2" SrcPort 1 DstBlock "mult" DstPort 2 } } } Block { BlockType SubSystem Name "reverse2nmp" SID "1" Ports [3, 1] Position [25, 15, 90, 115] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "n" MaskStyleString "edit" MaskVariables "WIDTH=@1;" MaskTunableValueString "on" MaskEnableString "on" MaskVisibilityString "on" MaskToolTipString "on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "WIDTH" System { Name "reverse2nmp" Location [545, 334, 1225, 974] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In2nm" SID "2" Position [35, 138, 65, 152] IconDisplay "Port number" } Block { BlockType Inport Name "In2n" SID "3" Position [35, 183, 65, 197] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In2np" SID "4" Position [35, 228, 65, 242] Port "3" IconDisplay "Port number" } Block { BlockType SubSystem Name "reverse2n" SID "5" Ports [3, 1] Position [230, 123, 330, 257] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "reverse2n" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "57" Block { BlockType Inport Name "in2nm" SID "5::28" Position [20, 101, 40, 119] ZOrder 15 IconDisplay "Port number" } Block { BlockType Inport Name "in2n" SID "5::23" Position [20, 136, 40, 154] ZOrder 14 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "in2np" SID "5::29" Position [20, 171, 40, 189] ZOrder 16 Port "3" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "5::19" Ports [1, 1] Position [270, 205, 320, 245] ZOrder 10 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "5::18" Tag "Stateflow S-Function resedue_lib 8" Ports [3, 2] Position [180, 104, 230, 206] ZOrder 9 FunctionName "sf_sfun" Parameters "WIDTH" PortCounts "[3 2]" EnableBusSupport on Port { PortNumber 2 Name "z" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "5::21" Position [460, 216, 480, 234] ZOrder 12 } Block { BlockType Outport Name "z" SID "5::22" Position [460, 101, 480, 119] ZOrder 13 IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "z" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "z" DstPort 1 } Line { SrcBlock "in2np" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "in2n" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "in2nm" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "Out" SID "6" Position [430, 183, 460, 197] IconDisplay "Port number" } Line { SrcBlock "In2np" SrcPort 1 DstBlock "reverse2n" DstPort 3 } Line { SrcBlock "In2n" SrcPort 1 DstBlock "reverse2n" DstPort 2 } Line { SrcBlock "In2nm" SrcPort 1 DstBlock "reverse2n" DstPort 1 } Line { SrcBlock "reverse2n" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "reverseReIm" SID "90" Ports [2, 2] Position [450, 97, 485, 128] LibraryVersion "1.37" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wmod|P|Qp" MaskStyleString "edit,edit,edit" MaskVariables "Wmod=@1;P=@2;Qp=@3;" MaskTunableValueString "on,on,on" MaskCallbackString "||" MaskEnableString "on,on,on" MaskVisibilityString "on,on,on" MaskToolTipString "on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wmod|P|Qp" System { Name "reverseReIm" Location [812, 183, 1492, 823] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v" SID "91" Position [100, 238, 130, 252] IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "92" Position [100, 268, 130, 282] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "reverse" SID "93" Ports [2, 2] Position [230, 230, 300, 290] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "reverse" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "45" Block { BlockType Inport Name "v" SID "93::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v_" SID "93::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "93::2" Ports [1, 1] Position [270, 180, 320, 220] ZOrder 70 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "93::1" Tag "Stateflow S-Function resedue_lib 12" Ports [2, 3] Position [180, 100, 230, 180] ZOrder 69 FunctionName "sf_sfun" Parameters "P,Qp,Wmod" PortCounts "[2 3]" EnableBusSupport off Port { PortNumber 2 Name "Re" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Im" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "93::4" Position [460, 191, 480, 209] ZOrder 72 } Block { BlockType Outport Name "Re" SID "93::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "93::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock "v" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "Re" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "Re" DstPort 1 } Line { Name "Im" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "Im" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Outport Name "Re" SID "94" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "Im" SID "95" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "reverse" SrcPort 1 Points [50, 0; 0, -15] DstBlock "Re" DstPort 1 } Line { SrcBlock "v" SrcPort 1 DstBlock "reverse" DstPort 1 } Line { SrcBlock "v_" SrcPort 1 DstBlock "reverse" DstPort 2 } Line { SrcBlock "reverse" SrcPort 2 DstBlock "Im" DstPort 1 } } } Block { BlockType SubSystem Name "sumReIm" SID "74" Ports [4, 2] Position [315, 166, 375, 269] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wpos|Wmod|P|Qp|Qm" MaskStyleString "edit,edit,edit,edit,edit" MaskVariables "Wpos=@1;Wmod=@2;P=@3;Qp=@4;Qm=@5;" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wpos|Wmod|P|Qp|Qm" System { Name "sumReIm" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v1" SID "75" Position [50, 218, 80, 232] IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "76" Position [50, 248, 80, 262] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "77" Position [55, 273, 85, 287] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "78" Position [55, 303, 85, 317] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "sum" SID "79" Ports [4, 2] Position [230, 232, 300, 293] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "sum" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "47" Block { BlockType Inport Name "v1" SID "79::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v1_" SID "79::43" Position [20, 136, 40, 154] ZOrder 30 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "79::46" Position [20, 171, 40, 189] ZOrder 33 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "v2_" SID "79::47" Position [20, 206, 40, 224] ZOrder 34 Port "4" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "79::32" Ports [1, 1] Position [270, 280, 320, 320] ZOrder 19 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "79::31" Tag "Stateflow S-Function resedue_lib 3" Ports [4, 3] Position [180, 127, 230, 278] ZOrder 18 FunctionName "sf_sfun" Parameters "P,Qm,Qp,Wmod" PortCounts "[4 3]" EnableBusSupport on Port { PortNumber 2 Name "sumv" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "sumv_" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "79::34" Position [460, 291, 480, 309] ZOrder 21 } Block { BlockType Outport Name "sumv" SID "79::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "79::45" Position [460, 136, 480, 154] ZOrder 32 Port "2" IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "sumv_" Labels [0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "sumv_" DstPort 1 } Line { Name "sumv" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "sumv" DstPort 1 } Line { SrcBlock "v2_" SrcPort 1 DstBlock " SFunction " DstPort 4 } Line { SrcBlock "v2" SrcPort 1 DstBlock " SFunction " DstPort 3 } Line { SrcBlock "v1_" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v1" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "sumv" SID "80" Position [435, 223, 465, 237] IconDisplay "Port number" } Block { BlockType Outport Name "sumv_" SID "81" Position [435, 268, 465, 282] Port "2" IconDisplay "Port number" } Line { SrcBlock "v2_" SrcPort 1 Points [60, 0; 0, -25] DstBlock "sum" DstPort 4 } Line { SrcBlock "v2" SrcPort 1 Points [60, 0; 0, -10] DstBlock "sum" DstPort 3 } Line { SrcBlock "sum" SrcPort 1 Points [50, 0; 0, -20] DstBlock "sumv" DstPort 1 } Line { SrcBlock "v1" SrcPort 1 Points [130, 0] DstBlock "sum" DstPort 1 } Line { SrcBlock "v1_" SrcPort 1 DstBlock "sum" DstPort 2 } Line { SrcBlock "sum" SrcPort 2 Points [0, -5] DstBlock "sumv_" DstPort 1 } } } Block { BlockType SubSystem Name "sum_mod" SID "101" Ports [2, 1] Position [620, 199, 655, 241] TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "WIDTH of input value" MaskDescription "Choose n for module 2^n-1" MaskHelp "help help help SOS!!!" MaskPromptString "Wmod|P" MaskStyleString "edit,edit" MaskVariables "Wmod=@1;P=@2;" MaskTunableValueString "on,on" MaskCallbackString "|" MaskEnableString "on,on" MaskVisibilityString "on,on" MaskToolTipString "on,on" MaskInitialization "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "Wmod|P" System { Name "sum_mod" Location [203, 186, 883, 826] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "v1" SID "102" Position [55, 243, 85, 257] IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "103" Position [55, 273, 85, 287] Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "sum" SID "104" Ports [2, 1] Position [230, 234, 300, 296] ZOrder 1 LibraryVersion "1.1" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off SFBlockType "MATLAB Function" MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('private/" "eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "sum" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "57" Block { BlockType Inport Name "v1" SID "104::42" Position [20, 101, 40, 119] ZOrder 29 IconDisplay "Port number" } Block { BlockType Inport Name "v2" SID "104::46" Position [20, 136, 40, 154] ZOrder 33 Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "104::49" Ports [1, 1] Position [270, 205, 320, 245] ZOrder 36 Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "104::48" Tag "Stateflow S-Function resedue_lib 11" Ports [2, 2] Position [180, 104, 230, 206] ZOrder 35 FunctionName "sf_sfun" Parameters "P,Wmod" PortCounts "[2 2]" EnableBusSupport off Port { PortNumber 2 Name "sum" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "104::51" Position [460, 216, 480, 234] ZOrder 38 } Block { BlockType Outport Name "sum" SID "104::44" Position [460, 101, 480, 119] ZOrder 31 IconDisplay "Port number" } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { Name "sum" Labels [0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "sum" DstPort 1 } Line { SrcBlock "v2" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { SrcBlock "v1" SrcPort 1 DstBlock " SFunction " DstPort 1 } } } Block { BlockType Outport Name "sumv" SID "105" Position [425, 258, 455, 272] IconDisplay "Port number" } Line { SrcBlock "v2" SrcPort 1 DstBlock "sum" DstPort 2 } Line { SrcBlock "sum" SrcPort 1 DstBlock "sumv" DstPort 1 } Line { SrcBlock "v1" SrcPort 1 DstBlock "sum" DstPort 1 } } } } } # Finite State Machines # # Stateflow Version 7.6 (R2011b) dated Jan 25 2012, 13:50:40 # # Stateflow { machine { id 1 name "resedue_lib" created "04-Jun-2014 17:52:05" isLibrary 1 firstTarget 151 sfVersion 76014001.00040001 } chart { id 2 name "mul2nmp/mul2n" windowPosition [660.75 -81.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 3 0 0] firstTransition 5 firstJunction 4 viewObj 2 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 14 decomposition CLUSTER_CHART type EML_CHART firstData 6 chartFileNumber 1 disableImplicitCasting 1 eml { name "fcn" } } state { id 3 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 2 treeNode [2 0 0 0] superState SUBCHART subviewer 2 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(A, B, WIDTH)\n\n a = fi(A,0,WIDTH,0,'overflowmode', 'wrap');\n medi = fi(0" ",0,WIDTH,0,'overflowmode', 'wrap');\n \n p = fi(zeros(1,WIDTH),0,WIDTH,0);\n \n temp = fi(0,0,WIDTH," "0,'overflowmode', 'wrap');\n temp1 = fi(0,0,WIDTH+1,0,'overflowmode', 'wrap');\n \n for m = 1:WIDTH\n%%" "% temp = bitshift( bitand(bitshift(fi(2^WIDTH-1,0,WIDTH,0),1-m) , bitsliceget(A,WIDTH,1)) , m-1 );\n " "temp = bitshift( a , m-1 );\n temp = temp * bitget(B,m);\n%%% p1(m) = bitsliceget(bitshift( bitand" "(bitshift(fi(2^WIDTH-1,0,WIDTH,0),WIDTH-m) , bitsliceget(A,WIDTH,1)) , m ) * bitget(B,m));\n p(m) = fi(te" "mp,0,WIDTH,0);\n medi = fi(medi + p(m),0,WIDTH,0,'overflowmode', 'wrap');\n end\n \n z = bitslic" "eget(medi,WIDTH,1);\nend \n\n% // multipier 2n\n% module mul2n (A, B, out);\n% input [8:0] A;\n% input [8:0] B" ";\n% output [8:0] out;\n% wire [12:0] intermediate;\n% wire [8:0] p0, p1, p2, p3, p4, p5, p6, p7, p8; \n% \n%" " assign p0 = A[8:0] * B[0]; \n% assign p1 = (A[7:0] << 1) * B[1]; \n% assign p2 = (A[6:0] << 2) * B[2]; \n% " "assign p3 = (A[5:0] << 3) * B[3]; \n% assign p4 = (A[4:0] << 4) * B[4]; \n% assign p5 = (A[3:0] << 5) * B[5]; " "\n% assign p6 = (A[2:0] << 6) * B[6]; \n% assign p7 = (A[1:0] << 7) * B[7]; \n% assign p8 = (A[0] << 8) * B[8" "]; \n% assign intermediate = p0 + p1 + p2 + p3 + p4 + p5 + p6 + p7 + p8;\n% assign out = intermediate[8:0];\n%" " endmodule" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 4 position [23.5747 49.5747 7] chart 2 linkNode [2 0 0] subviewer 2 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 5 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 4 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 2 linkNode [2 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 2 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 6 ssIdNumber 4 name "A" linkNode [2 0 7] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 7 ssIdNumber 6 name "z" linkNode [2 6 8] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 8 ssIdNumber 7 name "B" linkNode [2 7 9] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 9 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [2 8 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE enumType "" wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 10 name "mul2nmp/mul2n" machine 1 chart 2 } chart { id 11 name "forwardReIm/forward" windowPosition [615.75 -36.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 12 0 0] firstTransition 14 firstJunction 13 viewObj 11 machine 1 ssIdHighWaterMark 21 decomposition CLUSTER_CHART type EML_CHART firstData 15 chartFileNumber 2 disableImplicitCasting 1 eml { name "fcn" } } state { id 12 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 11 treeNode [11 0 0 0] superState SUBCHART subviewer 11 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [v, v_] = fcn(x,y,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n qm_fix = fi(Qm,0," "Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n\n v = fi(mod(x+qp_fix*y,p_fix),0,Wmod,0);\n v_ = fi(mod(x+qm_fix*y" ",p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 13 position [23.5747 49.5747 7] chart 11 linkNode [11 0 0] subviewer 11 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 14 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 13 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 11 linkNode [11 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 11 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 15 ssIdNumber 4 name "x" linkNode [11 0 16] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_INT16_TYPE wordLength "Wpos" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "Inherit: Same as Simulink" } data { id 16 ssIdNumber 6 name "v" linkNode [11 15 17] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 17 ssIdNumber 11 name "y" description "xcdfghb" linkNode [11 16 18] scope INPUT_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "Wpos" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 18 ssIdNumber 15 name "v_" linkNode [11 17 19] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 19 ssIdNumber 17 name "Wmod" linkNode [11 18 20] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 20 ssIdNumber 19 name "P" linkNode [11 19 21] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 21 ssIdNumber 20 name "Qp" linkNode [11 20 22] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 22 ssIdNumber 21 name "Qm" linkNode [11 21 0] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 23 name "forwardReIm/forward" machine 1 chart 11 } chart { id 24 name "sumReIm/sum" windowPosition [615.75 -36.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 25 0 0] firstTransition 27 firstJunction 26 viewObj 24 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 25 decomposition CLUSTER_CHART type EML_CHART firstData 28 chartFileNumber 3 disableImplicitCasting 1 eml { name "fcn" } } state { id 25 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 24 treeNode [24 0 0 0] superState SUBCHART subviewer 24 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [sumv, sumv_] = fcn(v1,v1_,v2,v2_,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n q" "m_fix = fi(Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n \n if( (v1+v2) >= p_fix)\n sumv = fi( v1+v2" " - p_fix,0,Wmod,0);\n else \n sumv = fi( v1+v2,0,Wmod,0);\n end\n \n if( (v1_+v2_) >= p_fix)\n" " sumv_ = fi( v1_+v2_ - p_fix,0,Wmod,0);\n else \n sumv_ = fi( v1_+v2_,0,Wmod,0);\n end\n " "\n %sumv_ = fi(mod((v1_+v2_),p_fix),0,Wmod,0);\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 26 position [23.5747 49.5747 7] chart 24 linkNode [24 0 0] subviewer 24 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 27 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 26 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 24 linkNode [24 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 24 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 28 ssIdNumber 6 name "v1" linkNode [24 0 29] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 29 ssIdNumber 15 name "v1_" linkNode [24 28 30] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 30 ssIdNumber 24 name "v2" linkNode [24 29 31] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 31 ssIdNumber 25 name "v2_" linkNode [24 30 32] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 32 ssIdNumber 17 name "Wmod" linkNode [24 31 33] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 33 ssIdNumber 19 name "P" linkNode [24 32 34] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 34 ssIdNumber 20 name "Qp" linkNode [24 33 35] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 35 ssIdNumber 21 name "Qm" linkNode [24 34 36] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 36 ssIdNumber 22 name "sumv" linkNode [24 35 37] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 37 ssIdNumber 23 name "sumv_" linkNode [24 36 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 38 name "sumReIm/sum" machine 1 chart 24 } chart { id 39 name "multReIm/mult" windowPosition [630.75 -51.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 40 0 0] firstTransition 42 firstJunction 41 viewObj 39 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 25 decomposition CLUSTER_CHART type EML_CHART firstData 43 chartFileNumber 4 disableImplicitCasting 1 eml { name "fcn" } } state { id 40 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 39 treeNode [39 0 0 0] superState SUBCHART subviewer 39 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [sumv, sumv_] = fcn(v1,v1_,v2,v2_,Wmod,P,Qp,Qm)\n\n qp_fix = fi(Qp,0,Wmod,0);\n q" "m_fix = fi(Qm,0,Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n\n% sumv = fi(mod((v1*v2),p_fix),0,Wmod,0);\n% sumv" "_ = fi(mod((v1_*v2_),p_fix),0,Wmod,0);\n\n sumv = fi(res((v1*v2),P,Wmod),0,Wmod,0);\n sumv_ = fi(res((v1_*" "v2_),P,Wmod),0,Wmod,0);\n \nend\n\nfunction z = res(a,module,Wmod)\n for k = 1:module\n if(a > modu" "le)\n a = fi(a - module,0,Wmod*2,0);\n end\n end\n z = a;\nend\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 41 position [23.5747 49.5747 7] chart 39 linkNode [39 0 0] subviewer 39 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 42 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 41 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 39 linkNode [39 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 39 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 43 ssIdNumber 6 name "v1" linkNode [39 0 44] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 44 ssIdNumber 15 name "v1_" linkNode [39 43 45] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 45 ssIdNumber 24 name "v2" linkNode [39 44 46] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 46 ssIdNumber 25 name "v2_" linkNode [39 45 47] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 47 ssIdNumber 17 name "Wmod" linkNode [39 46 48] scope PARAMETER_DATA paramIndexForInitFromWorkspace 3 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 48 ssIdNumber 19 name "P" linkNode [39 47 49] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 49 ssIdNumber 20 name "Qp" linkNode [39 48 50] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 50 ssIdNumber 21 name "Qm" linkNode [39 49 51] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 51 ssIdNumber 22 name "sumv" linkNode [39 50 52] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 52 ssIdNumber 23 name "sumv_" linkNode [39 51 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 53 name "multReIm/mult" machine 1 chart 39 } chart { id 54 name "mul2nmp/mul2nm" windowPosition [645.75 -66.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 55 0 0] firstTransition 57 firstJunction 56 viewObj 54 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 14 decomposition CLUSTER_CHART type EML_CHART firstData 58 chartFileNumber 5 disableImplicitCasting 1 eml { name "fcn" } } state { id 55 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 54 treeNode [54 0 0 0] superState SUBCHART subviewer 54 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(A,B,WIDTH)\n\n medi = fi(0,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');\n" " \n p = fi(zeros(1,WIDTH),0,WIDTH,0);\n \n temp = fi(0,0,WIDTH,0);\n \n\n% p(1) = bitsliceget(" " (A*bitget(B,1)), WIDTH,1) ;\n\n for m = 1:WIDTH\n temp = fi(A*bitget(B,m),0,WIDTH,0,'overflowmode', '" "wrap');\n% p(m) = bitconcat( bitsliceget( temp, WIDTH-m+1,1) , bitsliceget( temp, WIDTH, WIDTH - m + 2) )" ";\n% temp = fi( temp, 0, WIDTH-m+1,0,'overflowmode', 'wrap');\n% p(m) = bitconcat( fi( temp, 0, WI" "DTH-m+1,0,'overflowmode', 'wrap') , fi( bitshift(temp,WIDTH-m+1), 0, m-1,0,'overflowmode', 'wrap') );\n p" "(m) = bitrol(temp,m-1);\n\n medi = fi(medi + p(m),0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');\n e" "nd\n \n z = bitsliceget(mod(medi,WIDTH),WIDTH,1);\n% z = bitsliceget(medi,WIDTH,1);\nend \n \n\nfunc" "tion z = mod(medi,WIDTH)\n flag = fi(0,0,1,0);\n z = fi(0,0,WIDTH,0,'overflowmode', 'wrap');\n for m = " "1:WIDTH\n if(flag == 0)\n z = fi(medi - fi((m-1)*(2^WIDTH-1),0,WIDTH+log2(WIDTH)+1,0),0,WIDTH," "0,'overflowmode', 'wrap');\n end\n if( medi < fi(m*(2^WIDTH-1),0,WIDTH+log2(WIDTH)+1,0) )\n " " flag = fi(1,0,1,0);\n end\n end\nend\n\n\n% // multiplier 2nm1\n% \n% module mul2nm (a, b, out); /" "/ Умножитель \n% \n% input [8:0] a, b; \n% wire [12:0] intermediate; \n% output [8:0] out; \n" "% \n% wire [8:0] p0, p1, p2, p3, p4, p5, p6, p7, p8; \n% \n% // ФОРМИРОВАНИЕ ЧАСТИЧНЫХ П" "РОИЗВЕДЕНИЙ \n% \n% assign p0 = a[8:0] * b[0]; \n% assign p1 = {(a[7:0]*b[1]), a[8]*b[1]}; \n% as" "sign p2 = {(a[6:0]*b[2]), a[8:7]*b[2]}; \n% assign p3 = {(a[5:0]*b[3]), a[8:6]*b[3]}; \n% assign p4 = {(a[4:0]" "*b[4]), a[8:5]*b[4]}; \n% assign p5 = {(a[3:0]*b[5]), a[8:4]*b[5]}; \n% assign p6 = {(a[2:0]*b[6]), a[8:3]*b[6" "]}; \n% assign p7 = {(a[1:0]*b[7]), a[8:2]*b[7]}; \n% assign p8 = {(a[0]*b[8]), a[8:1]*b[8]}; \n% \n% assign" " intermediate = p0 + p1 + p2 + p3 + p4 + p5 + p6 + p7 + p8;\n% mod_511_4591 mod(intermediate, out); \n% \n% end" "module\n% \n% // Faster but more area\n% module mod_511_4591 (in, out);\n% input [12:0] in;\n% output reg [8:0" "] out;\n% always @ (in)\n% begin\n% if (in < 9'd511)\n% begin\n% out = in;\n% end\n% else if (in < " "10'd1022)\n% begin\n% out = in - 9'd511;\n% end\n% else if (in < 11'd1533)\n% begin\n% out = in - " "10'd1022;\n% end\n% else if (in < 11'd2044)\n% begin\n% out = in - 11'd1533;\n% end\n% else if (in " "< 12'd2555)\n% begin\n% out = in - 11'd2044;\n% end\n% else if (in < 12'd3066)\n% begin\n% out = i" "n - 12'd2555;\n% end\n% else if (in < 12'd3577)\n% begin\n% out = in - 12'd3066;\n% end\n% else if " "(in < 12'd4088)\n% begin\n% out = in - 12'd3577;\n% end\n% else\n% begin\n% out = in - 12'd4088;\n" "% end\n% end\n% endmodule" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 56 position [23.5747 49.5747 7] chart 54 linkNode [54 0 0] subviewer 54 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 57 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 56 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 54 linkNode [54 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 54 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 58 ssIdNumber 4 name "A" linkNode [54 0 59] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 59 ssIdNumber 6 name "z" linkNode [54 58 60] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 60 ssIdNumber 7 name "B" linkNode [54 59 61] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 61 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [54 60 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 62 name "mul2nmp/mul2nm" machine 1 chart 54 } chart { id 63 name "mul2nmp/mul2np" windowPosition [675.75 -96.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 64 0 0] firstTransition 66 firstJunction 65 viewObj 63 machine 1 ssIdHighWaterMark 14 decomposition CLUSTER_CHART type EML_CHART firstData 67 chartFileNumber 6 disableImplicitCasting 1 eml { name "fcn" } } state { id 64 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 63 treeNode [63 0 0 0] superState SUBCHART subviewer 63 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(A,B,WIDTH)\n\n medi = fi(WIDTH+2,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wr" "ap');\n \n p = fi(zeros(1,WIDTH+1),0,WIDTH+1,0);\n nA = fi(zeros(1,WIDTH),0,WIDTH,0);\n \n invA =" " fi(0,0,WIDTH,0);\n invB = fi(0,0,WIDTH,0);\n pall = fi(0,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');" "\n \n temp1 = fi(0,0,WIDTH,0);\n temp2 = fi(0,0,WIDTH,0);\n temp3 = fi(0,1,WIDTH+1,0);\n\n invA =" " bitcmp(A);\n invB = bitcmp(B);\n \n \n \n for m = 1:WIDTH\n temp1 = bitsliceget(A,WIDTH,1" ");\n temp1 = bitrol(temp1,m-1);\n% temp3 = fi(2^(m-1)-1,0,WIDTH,0);\n temp3 = fi(bitshift(f" "i(1,0,WIDTH,0),m-1)-1,0,WIDTH,0);\n temp2 = bitand( bitcmp(temp1) , temp3 );\n temp1 = bitand( tem" "p1 , bitcmp(temp3));\n nA(m) = bitor( temp1 , temp2);\n\n\n end\n for m = 1:WIDTH\n% p(m) = " "bitget(B,m) * nA(m) + bitget(invB,m) * fi(2^(m-1)-1,0,WIDTH,0);\n p(m) = bitget(B,m) * nA(m) + bitget(inv" "B,m) * fi(bitshift(fi(1,0,WIDTH,0),m-1)-1,0,WIDTH,0);\n\n medi = fi(medi + p(m),0,WIDTH+log2(WIDTH)+1,0,'" "overflowmode', 'wrap');\n end\n \n if( (A == fi(2^WIDTH,0,WIDTH+1,0)) && (B == fi(2^WIDTH,0,WIDTH+1,0))" " )\n pall = fi(1,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');\n else if (A == fi(2^WIDTH,0,WIDTH+1" ",0))\n pall = fi(invB+2,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');\n else if (B == fi(2^WID" "TH,0,WIDTH+1,0))\n pall = fi(invA+2,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');\n el" "se\n pall = fi(medi,0,WIDTH+log2(WIDTH)+1,0,'overflowmode', 'wrap');\n end\n e" "nd\n end\n z = bitsliceget(mod(pall,WIDTH),WIDTH+1,1);\n% z = bitsliceget(medi,WIDTH,1);\nend \n \n\n" "function z = mod(pall,WIDTH)\n flag = fi(0,0,1,0);\n z = fi(0,0,WIDTH+1,0,'overflowmode', 'wrap');\n fo" "r m = 1:WIDTH\n if(flag == 0)\n z = fi(pall - fi((m-1)*(2^WIDTH+1),0,WIDTH+log2(WIDTH)+1,0),0," "WIDTH+1,0,'overflowmode', 'wrap');\n end\n if( pall < fi(m*(2^WIDTH+1),0,WIDTH+log2(WIDTH)+1,0) )\n" " flag = fi(1,0,1,0); \n end\n end\nend\n \n%// Faster but more area\n% module mod_513_4610" " (in, out);\n% input [12:0] in;\n% output reg [9:0] out;\n% always @ (in)\n% begin\n% if (in < 10'd513)\n%" " begin\n% out = in;\n% end\n% else if (in < 11'd1026)\n% begin\n% out = in - 10'd513;\n% end\n% " " else if (in < 11'd1539)\n% begin\n% out = in - 11'd1026;\n% end\n% else if (in < 12'd2052)\n% begin" "\n% out = in - 11'd1539;\n% end\n% else if (in < 12'd2565)\n% begin\n% out = in - 12'd2052;\n% end" "\n% else if (in < 12'd3078)\n% begin\n% out = in - 12'd2565;\n% end\n% else if (in < 12'd3591)\n% b" "egin\n% out = in - 12'd3078;\n% end\n% else if (in < 13'd4104)\n% begin\n% out = in - 12'd3591;\n% " " end\n% else\n% begin\n% out = in - 13'd4104;\n% end\n% end\n% endmodule\n\n\n% // multiplier 2np1\n% " "\n% module mul2np (A, B, out);\n% input [9:0] A;\n% input [9:0] B;\n% output [9:0] out;\n% wire [8:0] invA;\n" "% wire [8:0] invB;\n% wire [8:0] nA_0; \n% wire [9:0] P_0;\n% wire [8:0] nA_1; \n% wire [9:0] P_1;\n% wire" " [8:0] nA_2; \n% wire [9:0] P_2;\n% wire [8:0] nA_3; \n% wire [9:0] P_3;\n% wire [8:0] nA_4; \n% wire [9:0]" " P_4;\n% wire [8:0] nA_5; \n% wire [9:0] P_5;\n% wire [8:0] nA_6; \n% wire [9:0] P_6;\n% wire [8:0] nA_7; \n" "% wire [9:0] P_7;\n% wire [8:0] nA_8; \n% wire [9:0] P_8;\n% reg [12:0] P_ALL;\n% \n% assign invA[0] = ~A[" "0]; \n% assign invA[1] = ~A[1]; \n% assign invA[2] = ~A[2]; \n% assign invA[3] = ~A[3]; \n% assign invA[4] =" " ~A[4]; \n% assign invA[5] = ~A[5]; \n% assign invA[6] = ~A[6]; \n% assign invA[7] = ~A[7]; \n% assign invA[" "8] = ~A[8];\n% \n% assign invB[0] = ~B[0]; \n% assign invB[1] = ~B[1]; \n% assign invB[2] = ~B[2]; \n% assi" "gn invB[3] = ~B[3]; \n% assign invB[4] = ~B[4]; \n% assign invB[5] = ~B[5]; \n% assign invB[6] = ~B[6]; \n% " "assign invB[7] = ~B[7]; \n% assign invB[8] = ~B[8];\n% \n% assign nA_0[0] = A[0];\n% assign nA_0[1] = A[1];\n" "% assign nA_0[2] = A[2];\n% assign nA_0[3] = A[3];\n% assign nA_0[4] = A[4];\n% assign nA_0[5] = A[5];\n% a" "ssign nA_0[6] = A[6];\n% assign nA_0[7] = A[7];\n% assign nA_0[8] = A[8];\n% assign nA_1[0] = ~A[8];\n% assi" "gn nA_1[1] = A[0];\n% assign nA_1[2] = A[1];\n% assign nA_1[3] = A[2];\n% assign nA_1[4] = A[3];\n% assign n" "A_1[5] = A[4];\n% assign nA_1[6] = A[5];\n% assign nA_1[7] = A[6];\n% assign nA_1[8] = A[7];\n% assign nA_2[" "0] = ~A[7];\n% assign nA_2[1] = ~A[8];\n% assign nA_2[2] = A[0];\n% assign nA_2[3] = A[1];\n% assign nA_2[4]" " = A[2];\n% assign nA_2[5] = A[3];\n% assign nA_2[6] = A[4];\n% assign nA_2[7] = A[5];\n% assign nA_2[8] = A" "[6];\n% assign nA_3[0] = ~A[6];\n% assign nA_3[1] = ~A[7];\n% assign nA_3[2] = ~A[8];\n% assign nA_3[3] = A[" "0];\n% assign nA_3[4] = A[1];\n% assign nA_3[5] = A[2];\n% assign nA_3[6] = A[3];\n% assign nA_3[7] = A[4];\n" "% assign nA_3[8] = A[5];\n% assign nA_4[0] = ~A[5];\n% assign nA_4[1] = ~A[6];\n% assign nA_4[2] = ~A[7];\n%" " assign nA_4[3] = ~A[8];\n% assign nA_4[4] = A[0];\n% assign nA_4[5] = A[1];\n% assign nA_4[6] = A[2];\n% a" "ssign nA_4[7] = A[3];\n% assign nA_4[8] = A[4];\n% assign nA_5[0] = ~A[4];\n% assign nA_5[1] = ~A[5];\n% ass" "ign nA_5[2] = ~A[6];\n% assign nA_5[3] = ~A[7];\n% assign nA_5[4] = ~A[8];\n% assign nA_5[5] = A[0];\n% assi" "gn nA_5[6] = A[1];\n% assign nA_5[7] = A[2];\n% assign nA_5[8] = A[3];\n% assign nA_6[0] = ~A[3];\n% assign " "nA_6[1] = ~A[4];\n% assign nA_6[2] = ~A[5];\n% assign nA_6[3] = ~A[6];\n% assign nA_6[4] = ~A[7];\n% assign " "nA_6[5] = ~A[8];\n% assign nA_6[6] = A[0];\n% assign nA_6[7] = A[1];\n% assign nA_6[8] = A[2];\n% assign nA_" "7[0] = ~A[2];\n% assign nA_7[1] = ~A[3];\n% assign nA_7[2] = ~A[4];\n% assign nA_7[3] = ~A[5];\n% assign nA_" "7[4] = ~A[6];\n% assign nA_7[5] = ~A[7];\n% assign nA_7[6] = ~A[8];\n% assign nA_7[7] = A[0];\n% assign nA_7" "[8] = A[1];\n% assign nA_8[0] = ~A[1];\n% assign nA_8[1] = ~A[2];\n% assign nA_8[2] = ~A[3];\n% assign nA_8[" "3] = ~A[4];\n% assign nA_8[4] = ~A[5];\n% assign nA_8[5] = ~A[6];\n% assign nA_8[6] = ~A[7];\n% assign nA_8[" "7] = ~A[8];\n% assign nA_8[8] = A[0];\n% \n% assign P_0 = (B[0]*nA_0);\n% assign P_1 = (B[1]*nA_1) + !B[1]*1'" "b1;\n% assign P_2 = (B[2]*nA_2) + !B[2]*2'b11;\n% assign P_3 = (B[3]*nA_3) + !B[3]*3'b111;\n% assign P_4 = (B" "[4]*nA_4) + !B[4]*4'b1111;\n% assign P_5 = (B[5]*nA_5) + !B[5]*5'b11111;\n% assign P_6 = (B[6]*nA_6) + !B[6]*6" "'b111111;\n% assign P_7 = (B[7]*nA_7) + !B[7]*7'b1111111;\n% assign P_8 = (B[8]*nA_8) + !B[8]*8'b11111111;\n% " "\n% mod_513_4610 mod(P_ALL, out);\n% \n% always @(*)\n% begin\n% if ((A == 10'd512) && (B == 10'd512))\n% " " P_ALL <= 1;\n% else if (A == 10'd512)\n% begin\n% P_ALL <= invB + 2;\n% end\n% else if (B == 10'd5" "12)\n% begin\n% P_ALL <= invA + 2;\n% end\n% else\n% begin\n% P_ALL <= P_0 + P_1 + P_2 + P_3 + P_4" " + P_5 + P_6 + P_7 + P_8 + 11;\n% end\n% end\n% \n% endmodule\n\n% // Faster but more area\n% module mod_513" "_4610 (in, out);\n% input [12:0] in;\n% output reg [9:0] out;\n% always @ (in)\n% begin\n% if (in < 10'd51" "3)\n% begin\n% out = in;\n% end\n% else if (in < 11'd1026)\n% begin\n% out = in - 10'd513;\n% en" "d\n% else if (in < 11'd1539)\n% begin\n% out = in - 11'd1026;\n% end\n% else if (in < 12'd2052)\n% " "begin\n% out = in - 11'd1539;\n% end\n% else if (in < 12'd2565)\n% begin\n% out = in - 12'd2052;\n% " " end\n% else if (in < 12'd3078)\n% begin\n% out = in - 12'd2565;\n% end\n% else if (in < 12'd3591)\n" "% begin\n% out = in - 12'd3078;\n% end\n% else if (in < 13'd4104)\n% begin\n% out = in - 12'd3591;" "\n% end\n% else\n% begin\n% out = in - 13'd4104;\n% end\n% end\n% endmodule\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 65 position [23.5747 49.5747 7] chart 63 linkNode [63 0 0] subviewer 63 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 66 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 65 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 63 linkNode [63 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 63 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 67 ssIdNumber 4 name "A" linkNode [63 0 68] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH+1" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH+1,0)" } data { id 68 ssIdNumber 6 name "z" linkNode [63 67 69] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 69 ssIdNumber 7 name "B" linkNode [63 68 70] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH+1" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH+1,0)" } data { id 70 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [63 69 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 71 name "mul2nmp/mul2np" machine 1 chart 63 } chart { id 72 name "reverse2nmp/reverse2n" windowPosition [525.75 53.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 73 0 0] firstTransition 75 firstJunction 74 viewObj 72 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 15 decomposition CLUSTER_CHART type EML_CHART firstData 76 chartFileNumber 8 disableImplicitCasting 1 eml { name "fcn" } } state { id 73 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 72 treeNode [72 0 0 0] superState SUBCHART subviewer 72 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(in2nm, in2n, in2np,WIDTH)\n\n\n x1 = fi(0,0,WIDTH+1,0);\n x2 = fi(0,0,WID" "TH,0);\n x3 = fi(0,0,WIDTH,0);\n \n a1 = fi(0,0,WIDTH*2,0);\n a2 = fi(0,0,WIDTH*2,0);\n a3 = fi(0" ",0,WIDTH*2,0);\n \n sum1 = fi(0,0,WIDTH*2,0);\n sum2 = fi(0,0,WIDTH*2,0);\n sum3 = fi(0,0,WIDTH*2,0)" ";\n\n z_prom = fi(0,0,WIDTH*3,0);\n \n x1 = in2np;\n x2 = in2n;\n x3 = in2nm;\n \n a1 = coe" "f_a1(x1,WIDTH);\n a2 = coef_a2(x2,WIDTH);\n a3 = coef_a3(x3,WIDTH);\n \n sum1 = sum_modulo(a2,a3,WID" "TH);\n sum2 = sub(a1,x1,WIDTH);\n sum3 = sum_modulo(sum1,sum2,WIDTH);\n \n z_prom = bitsliceget(bitc" "oncat(sum3,x2),WIDTH*3,1);\n \n \n z = z_prom;\n \nend\n\nfunction a1 = coef_a1(x1,WIDTH)\n a1 = " "fi(0,0,WIDTH*2,0);\n \n bx = fi(0,0,1,0);\n bx = bitxor(bitget(x1,WIDTH+1) , bitget(x1,1));\n a1 = b" "itconcat(bx , bitsliceget(x1,WIDTH,2) , bx , bitsliceget(x1,WIDTH,2));\nend\n \nfunction a2 = coef_a2(x2,WIDT" "H)\n a2 = fi(0,0,WIDTH*2,0);\n a2 = bitconcat( bitcmp(x2), fi(2^WIDTH - 1,0,WIDTH,0)); \nend\n\nfunction a" "3 = coef_a3(x3,WIDTH)\n a3 = fi(0,0,WIDTH*2,0);\n \n a3 = bitconcat(bitget(x3,1), x3, bitsliceget(x3,WI" "DTH,2));\nend\n\nfunction z = sum_modulo(u,v,WIDTH)\n sum = fi(0,0,2*WIDTH+1,0);\n sum1 = fi(0,0,2*WIDTH+" "1,0);\n\n sum = u + v;\n sum1 = sum + fi(1,0,2*WIDTH,0);\n\n if( bitget(sum1, 2*WIDTH+1) )\n z " "= bitsliceget(sum1,2*WIDTH,1);\n else\n z = bitsliceget(sum,2*WIDTH,1);\n end\nend\n\nfunction z = " "sub(a1,x1,WIDTH)\n z_prom = fi(0,0,WIDTH*2,0);\n \n z_prom = a1 - x1;\n z = bitsliceget(z_prom,WIDTH" "*2,1);\nend\n\n\n\n\n\n\n% module reverse_converter_513_512_511 (x1, x2, x3, out);\n% input [9:0] x1;\n% input" " [8:0] x2;\n% input [8:0] x3;\n% wire [17:0] a1;\n% wire [17:0] a2;\n% wire [17:0] a3;\n% wire [17:0] sum1;" "\n% wire [17:0] sum2;\n% wire [17:0] sum3;\n% output [26:0] out;\n% \n% coef_a1 ca1(x1,a1);\n% coef_a2 ca" "2(x2,a2);\n% coef_a3 ca3(x3,a3);\n% sum_modulo_262143 sm1(a2, a3, sum1);\n% sub_a1_x1 sm2(a1, x1, sum2);\n% " "sum_modulo_262143 sm3(sum1, sum2, sum3);\n% \n% assign out[0] = x2[0];\n% assign out[1] = x2[1];\n% assign o" "ut[2] = x2[2];\n% assign out[3] = x2[3];\n% assign out[4] = x2[4];\n% assign out[5] = x2[5];\n% assign out[6" "] = x2[6];\n% assign out[7] = x2[7];\n% assign out[8] = x2[8];\n% \n% assign out[9] = sum3[0];\n% assign ou" "t[10] = sum3[1];\n% assign out[11] = sum3[2];\n% assign out[12] = sum3[3];\n% assign out[13] = sum3[4];\n% a" "ssign out[14] = sum3[5];\n% assign out[15] = sum3[6];\n% assign out[16] = sum3[7];\n% assign out[17] = sum3[8" "];\n% assign out[18] = sum3[9];\n% assign out[19] = sum3[10];\n% assign out[20] = sum3[11];\n% assign out[21" "] = sum3[12];\n% assign out[22] = sum3[13];\n% assign out[23] = sum3[14];\n% assign out[24] = sum3[15];\n% a" "ssign out[25] = sum3[16];\n% assign out[26] = sum3[17];\n% \n% endmodule\n% \n% module coef_a3 (x3, a3);\n% i" "nput [8:0] x3;\n% output [17:0] a3;\n% assign a3[17] = x3[0];\n% assign a3[16] = x3[8];\n% assign a3[15] = x" "3[7];\n% assign a3[14] = x3[6];\n% assign a3[13] = x3[5];\n% assign a3[12] = x3[4];\n% assign a3[11] = x3[3]" ";\n% assign a3[10] = x3[2];\n% assign a3[9] = x3[1];\n% assign a3[8] = x3[0];\n% assign a3[7] = x3[8];\n% a" "ssign a3[6] = x3[7];\n% assign a3[5] = x3[6];\n% assign a3[4] = x3[5];\n% assign a3[3] = x3[4];\n% assign a3" "[2] = x3[3];\n% assign a3[1] = x3[2];\n% assign a3[0] = x3[1];\n% endmodule\n% \n% module coef_a2 (x2, a2);\n%" " input [8:0] x2;\n% output [17:0] a2;\n% assign a2[17] = ~x2[8];\n% assign a2[16] = ~x2[7];\n% assign a2[15" "] = ~x2[6];\n% assign a2[14] = ~x2[5];\n% assign a2[13] = ~x2[4];\n% assign a2[12] = ~x2[3];\n% assign a2[11" "] = ~x2[2];\n% assign a2[10] = ~x2[1];\n% assign a2[9] = ~x2[0];\n% assign a2[8] = 1;\n% assign a2[7] = 1;\n" "% assign a2[6] = 1;\n% assign a2[5] = 1;\n% assign a2[4] = 1;\n% assign a2[3] = 1;\n% assign a2[2] = 1;\n% " " assign a2[1] = 1;\n% assign a2[0] = 1;\n% endmodule\n% \n% module coef_a1 (x1, a1);\n% input [9:0] x1;\n% ou" "tput [17:0] a1;\n% wire bx;\n% \n% assign bx = x1[9] ^ x1[0];\n% assign a1[17] = bx;\n% assign a1[16] = x1[" "8];\n% assign a1[15] = x1[7];\n% assign a1[14] = x1[6];\n% assign a1[13] = x1[5];\n% assign a1[12] = x1[4];\n" "% assign a1[11] = x1[3];\n% assign a1[10] = x1[2];\n% assign a1[9] = x1[1];\n% assign a1[8] = bx;\n% assign" " a1[7] = x1[8];\n% assign a1[6] = x1[7];\n% assign a1[5] = x1[6];\n% assign a1[4] = x1[5];\n% assign a1[3] =" " x1[4];\n% assign a1[2] = x1[3];\n% assign a1[1] = x1[2];\n% assign a1[0] = x1[1];\n% \n% endmodule\n% \n% /" "/ Sum modulo (2^18 - 1) = 262143\n% module sum_modulo_262143 (in1, in2, out);\n% input [17:0] in1;\n% input [1" "7:0] in2;\n% output reg [17:0] out;\n% wire [18:0] data;\n% wire [18:0] data2;\n% assign data = in1 + in2;\n" "% assign data2 = in1 + in2 + 1;\n% always @(*)\n% begin\n% if (data2[18] == 1)\n% out <= data2[17:0];\n%" " else\n% out <= data[17:0];\n% end\n% endmodule\n% \n% module sub_a1_x1 (a1, x1, out);\n% input [17:0] a1" ";\n% input [9:0] x1;\n% output [17:0] out;\n% \n% assign out = a1 - x1;\n% \n% endmodule\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 74 position [23.5747 49.5747 7] chart 72 linkNode [72 0 0] subviewer 72 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 75 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 74 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 72 linkNode [72 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 72 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 76 ssIdNumber 4 name "in2nm" linkNode [72 0 77] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 77 ssIdNumber 6 name "z" linkNode [72 76 78] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 78 ssIdNumber 7 name "in2n" linkNode [72 77 79] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 79 ssIdNumber 15 name "in2np" linkNode [72 78 80] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "WIDTH+1" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH+1,0)" } data { id 80 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [72 79 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 81 name "reverse2nmp/reverse2n" machine 1 chart 72 } chart { id 82 name "forward2nmp/forward" windowPosition [525.75 53.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 83 0 0] firstTransition 85 firstJunction 84 viewObj 82 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 16 decomposition CLUSTER_CHART type EML_CHART firstData 86 chartFileNumber 9 disableImplicitCasting 1 eml { name "fcn" } } state { id 83 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 82 treeNode [82 0 0 0] superState SUBCHART subviewer 82 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [out2nm, out2n, out2np] = fcn(u,WIDTH)\n\n x0 = fi(0,0,WIDTH,0);\n x1 = fi(0,0,WI" "DTH,0);\n x2 = fi(0,0,WIDTH,0);\n x_prom_511 = fi(0,0,WIDTH+2,0);\n x_prom_513 = fi(0,0,WIDTH+2,0);\n\n" "\n x0 = bitsliceget(u,WIDTH,1);\n x1 = bitsliceget(u,2*WIDTH,WIDTH+1);\n x2 = bitsliceget(u,3*WIDTH,2*W" "IDTH+1);\n \n x_prom_511 = x0 + x1 + x2;\n out2nm = mod_511_1533(x_prom_511, WIDTH);\n \n out2n =" " x0;\n\n x_prom_513 = x0 + fi(2^WIDTH + 1,0,WIDTH+1,0) - x1 + x2;\n out2np = mod_513_1537(x_prom_513, WIDT" "H);\nend\n\nfunction z = mod_511_1533(x_prom_511, WIDTH)\n z_prom = fi(0,0,WIDTH,0);\n \n if (x_prom_51" "1 < fi(2^WIDTH - 1,0,WIDTH+1,0))\n z_prom = bitsliceget(x_prom_511,WIDTH,1);\n else if (x_prom_511 " "< fi(2^(WIDTH+1) - 2,0,WIDTH+1,0))\n z_prom = bitsliceget(x_prom_511 - fi(2^WIDTH - 1,0,WIDTH,0),WIDT" "H,1);\n else if(x_prom_511 < fi(2^(WIDTH+1) + 2^WIDTH - 3,0,WIDTH+2,0))\n z_prom = bitsliceget" "(x_prom_511 - fi(2^(WIDTH+1) - 2,0,WIDTH+1,0),WIDTH,1);\n else\n z_prom = bitsliceget(" "x_prom_511 - fi(2^(WIDTH+1) + 2^WIDTH - 3,0,WIDTH+2,0),WIDTH,1);\n end\n end\n end\n z =" " z_prom;\nend\n\n\nfunction z = mod_513_1537(x_prom_513, WIDTH)\n z_prom = fi(0,0,WIDTH+1,0);\n \n if (" "x_prom_513 < fi(2^WIDTH + 1,0,WIDTH+1,0))\n z_prom = bitsliceget(x_prom_513,WIDTH+1,1);\n else if (" "x_prom_513 < fi(2^(WIDTH+1) + 2,0,WIDTH+2,0))\n z_prom = bitsliceget(x_prom_513 - fi(2^WIDTH + 1,0,WI" "DTH+1,0),WIDTH+1,1);\n else\n z_prom = bitsliceget(x_prom_513 - fi(2^(WIDTH+1) + 2,0,WIDTH+2,0" "),WIDTH+1,1);\n end\n end\n z = z_prom;\nend\n\n\n% module forward_converter (x, x_mod513, x_mod512" ", x_mod511);\n% input [26:0] x; output [9:0] x_mod513; output [8:0] x_mod512; output\n% [8:0] x_mod511;\n% \n" "% wire [8:0] x0; wire [8:0] x1; wire [8:0] x2; assign x0 = x[8:0]; assign\n% x1 = x[17:9]; assign x2 = x[26:18" "]; wire [10:0] x_prom_511; assign\n% x_prom_511 = x0 + x1 + x2 ; mod_511_1533 mod1(x_prom_511, x_mod511);\n% w" "ire [10:0] x_prom_513; assign x_prom_513 = x0 + 10'd513 - x1 + x2 + 0;\n% mod_513_1537 mod2(x_prom_513, x_mod51" "3); assign x_mod512 = x[8:0];\n% endmodule\n% \n% module mod_511_1533 (in, out);\n% input [10:0] in; output reg" " [8:0] out; always @ (in) begin\n% if (in < 9'd511) begin\n% out = in;\n% end else if (in < 10'd1022) beg" "in\n% out = in - 9'd511;\n% end else if (in < 11'd1533) begin\n% out = in - 10'd1022;\n% end else begi" "n\n% out = in - 11'd1533;\n% end\n% end\n% endmodule\n% \n% module mod_513_1537 (in, out);\n% input [10:0" "] in; output reg [9:0] out; always @ (in) begin\n% if (in < 10'd513) begin\n% out = in;\n% end else if (i" "n < 11'd1026) begin\n% out = in - 10'd513;\n% end else begin\n% out = in - 11'd1026;\n% end\n% end\n%" " endmodule\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 84 position [23.5747 49.5747 7] chart 82 linkNode [82 0 0] subviewer 82 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 85 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 84 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 82 linkNode [82 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 82 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 86 ssIdNumber 4 name "u" linkNode [82 0 87] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH*3" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH*3,0)" } data { id 87 ssIdNumber 6 name "out2nm" linkNode [82 86 88] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 88 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [82 87 89] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 89 ssIdNumber 15 name "out2n" linkNode [82 88 90] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 90 ssIdNumber 16 name "out2np" linkNode [82 89 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 91 name "forward2nmp/forward" machine 1 chart 82 } chart { id 92 name "mult_mod/mult" windowPosition [660.75 -81.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 93 0 0] firstTransition 95 firstJunction 94 viewObj 92 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 25 decomposition CLUSTER_CHART type EML_CHART firstData 96 chartFileNumber 10 disableImplicitCasting 1 eml { name "fcn" } } state { id 93 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 92 treeNode [92 0 0 0] superState SUBCHART subviewer 92 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function mult = fcn(v1,v2,Wmod,P)\n\n p_fix = fi(P,0,Wmod,0);\n\n mult = fi(mod((v1*v2),p" "_fix),0,Wmod,0);\n\n% sumv = fi(res((v1*v2),P,Wmod),0,Wmod,0);\n% sumv_ = fi(res((v1_*v2_),P,Wmod),0,Wmod," "0);\n \nend\n% \n% function z = res(a,module,Wmod)\n% for k = 1:module\n% if(a > module)\n% " " a = fi(a - module,0,Wmod*2,0);\n% end\n% end\n% z = a;\n% end\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 94 position [23.5747 49.5747 7] chart 92 linkNode [92 0 0] subviewer 92 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 95 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 94 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 92 linkNode [92 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 92 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 96 ssIdNumber 6 name "v1" linkNode [92 0 97] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 97 ssIdNumber 24 name "v2" linkNode [92 96 98] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 98 ssIdNumber 17 name "Wmod" linkNode [92 97 99] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 99 ssIdNumber 19 name "P" linkNode [92 98 100] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 100 ssIdNumber 22 name "mult" linkNode [92 99 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 101 name "mult_mod/mult" machine 1 chart 92 } chart { id 102 name "sum_mod/sum" windowPosition [645.75 -66.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 103 0 0] firstTransition 105 firstJunction 104 viewObj 102 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 25 decomposition CLUSTER_CHART type EML_CHART firstData 106 chartFileNumber 11 disableImplicitCasting 1 eml { name "fcn" } } state { id 103 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 102 treeNode [102 0 0 0] superState SUBCHART subviewer 102 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function sum = fcn(v1,v2,Wmod,P)\n\n p_fix = fi(P,0,Wmod,0);\n \n if( (v1+v2) >= p_fix" ")\n sum = fi( v1+v2 - p_fix,0,Wmod,0);\n else \n sum = fi( v1+v2,0,Wmod,0);\n end\n \n% " " if( (v1_+v2_) >= p_fix)\n% sumv_ = fi( v1_+v2_ - p_fix,0,Wmod,0);\n% else \n% sumv_ = fi(" " v1_+v2_,0,Wmod,0);\n% end\n \n %sumv_ = fi(mod((v1_+v2_),p_fix),0,Wmod,0);\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 104 position [23.5747 49.5747 7] chart 102 linkNode [102 0 0] subviewer 102 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 105 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 104 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 102 linkNode [102 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 102 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 106 ssIdNumber 6 name "v1" linkNode [102 0 107] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "fixdt(0,Wmod,0)" } data { id 107 ssIdNumber 24 name "v2" linkNode [102 106 108] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_DOUBLE_TYPE wordLength "Wmod" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,Wmod,0)" } data { id 108 ssIdNumber 17 name "Wmod" linkNode [102 107 109] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 109 ssIdNumber 19 name "P" linkNode [102 108 110] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 110 ssIdNumber 22 name "sum" linkNode [102 109 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 111 name "sum_mod/sum" machine 1 chart 102 } chart { id 112 name "reverseReIm/reverse" windowPosition [765.75 -169.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 113 0 0] firstTransition 115 firstJunction 114 viewObj 112 machine 1 toolbarMode LIBRARY_TOOLBAR ssIdHighWaterMark 23 decomposition CLUSTER_CHART type EML_CHART firstData 116 chartFileNumber 12 disableImplicitCasting 1 eml { name "fcn" } } state { id 113 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 112 treeNode [112 0 0 0] superState SUBCHART subviewer 112 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [Re, Im] = fcn(v,v_,Wmod,P,Qp)\n\n% qp_fix = fi(Qp,0,Wmod,0);\n% qm_fix = fi(Qm,0" ",Wmod,0);\n p_fix = fi(P,0,Wmod,0);\n two = fi(2,0,Wmod,0);\n\n Re = fi(mod((v+v_) * rev(2,P) ,p_fix),0" ",Wmod,0);\n Im = fi(mod((p_fix+v-v_) * rev(2*Qp,P), p_fix),0,Wmod,0);\n\n \nend\n\n\n" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 114 position [23.5747 49.5747 7] chart 112 linkNode [112 0 0] subviewer 112 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 115 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 114 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 112 linkNode [112 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 112 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 116 ssIdNumber 6 name "v" linkNode [112 0 117] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 117 ssIdNumber 15 name "v_" linkNode [112 116 118] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 118 ssIdNumber 17 name "Wmod" linkNode [112 117 119] scope PARAMETER_DATA paramIndexForInitFromWorkspace 2 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 119 ssIdNumber 19 name "P" linkNode [112 118 120] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 120 ssIdNumber 20 name "Qp" linkNode [112 119 121] scope PARAMETER_DATA paramIndexForInitFromWorkspace 1 isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 121 ssIdNumber 22 name "Re" linkNode [112 120 122] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 122 ssIdNumber 23 name "Im" linkNode [112 121 0] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } instance { id 123 name "reverseReIm/reverse" machine 1 chart 112 } chart { id 124 name "add2nmp/add2n" windowPosition [570.75 8.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 125 0 0] firstTransition 127 firstJunction 126 viewObj 124 machine 1 ssIdHighWaterMark 14 decomposition CLUSTER_CHART type EML_CHART firstData 128 chartFileNumber 14 disableImplicitCasting 1 eml { name "fcn" } } state { id 125 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 124 treeNode [124 0 0 0] superState SUBCHART subviewer 124 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(A,B,WIDTH)\n\n sum = fi(0,0,WIDTH+1,0);\n\n sum = A + B;\n\n z = bitsl" "iceget(sum,WIDTH,1);\n \n\n\n% %// Sum modulo (2^6) = 64\n% module adder_64 (out, in1, in2, clk, reset, enabl" "e);\n% input clk;\n% input reset;\n% input enable;\n% input [5:0] in1;\n% input [5:0] in2;\n% output reg [" "5:0] out;\n% wire [6:0] data;\n% assign data = in1 + in2;\n% always @ (posedge clk)\n% begin\n% if (reset =" "= 1'b1) begin\n% out <= 0;\n% end\n% else if (enable == 1'b1) begin\n% out <= data[5:0];\n% end\n% end\n" "% endmodule" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 126 position [23.5747 49.5747 7] chart 124 linkNode [124 0 0] subviewer 124 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 127 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 126 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 124 linkNode [124 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 124 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 128 ssIdNumber 4 name "A" linkNode [124 0 129] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 129 ssIdNumber 6 name "z" linkNode [124 128 130] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 130 ssIdNumber 7 name "B" linkNode [124 129 131] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 131 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [124 130 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 132 name "add2nmp/add2n" machine 1 chart 124 } chart { id 133 name "add2nmp/add2nm" windowPosition [555.75 23.25 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 134 0 0] firstTransition 136 firstJunction 135 viewObj 133 machine 1 ssIdHighWaterMark 14 decomposition CLUSTER_CHART type EML_CHART firstData 137 chartFileNumber 17 disableImplicitCasting 1 eml { name "fcn" } } state { id 134 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 133 treeNode [133 0 0 0] superState SUBCHART subviewer 133 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(A,B,WIDTH)\n\n sum = fi(0,0,WIDTH+1,0);\n sum1 = fi(0,0,WIDTH+2,0);\n\nsu" "m = A + B;\nsum1 = sum + fi(1,0,WIDTH+1,0);\nif( bitget(sum1, WIDTH+1) )\n z = bitsliceget(sum1,WIDTH,1);\ne" "lse\n z = bitsliceget(sum,WIDTH,1);\nend\n \n\n\n\n% // Sum modulo (2^6 - 1) = 63\n% module sum_modulo_63 " "(in1, in2, out);\n% input [5:0] in1;\n% input [5:0] in2;\n% output reg [5:0] out;\n% wire [6:0] data;\n% wi" "re [6:0] data2;\n% assign data = in1 + in2;\n% assign data2 = in1 + in2 + 1;\n% always @(*)\n% begin\n% if" " (data2[6] == 1)\n% out <= data2[5:0];\n% else\n% out <= data[5:0];\n% end\n% endmodule" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 135 position [23.5747 49.5747 7] chart 133 linkNode [133 0 0] subviewer 133 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 136 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 135 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 133 linkNode [133 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 133 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 137 ssIdNumber 4 name "A" linkNode [133 0 138] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 138 ssIdNumber 6 name "z" linkNode [133 137 139] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 139 ssIdNumber 7 name "B" linkNode [133 138 140] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH,0)" } data { id 140 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [133 139 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 141 name "add2nmp/add2nm" machine 1 chart 133 } chart { id 142 name "add2nmp/add2np" windowPosition [585.75 -6.75 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1920 1080 1.25] treeNode [0 143 0 0] firstTransition 145 firstJunction 144 viewObj 142 machine 1 ssIdHighWaterMark 14 decomposition CLUSTER_CHART type EML_CHART firstData 146 chartFileNumber 18 disableImplicitCasting 1 eml { name "fcn" } } state { id 143 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 142 treeNode [142 0 0 0] superState SUBCHART subviewer 142 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function z = fcn(A,B,WIDTH)\n\n\n sum = fi(0,0,WIDTH+2,0);\n sub = fi(0,0,WIDTH+3,0);\n\n " " sum = A + B;\n sub = sum - fi(2^WIDTH+1,0,WIDTH+1,0);\nif(sum < 2^WIDTH+1)\n z = bitsliceget(sum,WIDTH+" "1,1);\nelse\n z = bitsliceget(sub,WIDTH+1,1);\nend\n \n\n\n% // Sum modulo (2^6 + 1) = 65\n% module adder_6" "5 (out, in1, in2, clk, reset, enable);\n% input clk;\n% input reset;\n% input enable;\n% input [6:0] in1;\n%" " input [6:0] in2;\n% output reg [6:0] out;\n% wire [7:0] data;\n% assign data = in1 + in2;\n% always @ (pos" "edge clk)\n% begin\n% if (reset == 1'b1) begin\n% out <= 0;\n% end\n% else if (enable == 1'b1) begin\n% " "if (data < 65)\n% out <= data[6:0];\n% else\n% out <= data - 65;\n% end\n% end\n% endmodule" editorLayout "100 M4x1[10 5 700 500]" } } junction { id 144 position [23.5747 49.5747 7] chart 142 linkNode [142 0 0] subviewer 142 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 145 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 144 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 142 linkNode [142 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 142 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 146 ssIdNumber 4 name "A" linkNode [142 0 147] scope INPUT_DATA paramIndexForInitFromWorkspace 1 machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE wordLength "WIDTH+1" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED } dataType "fixdt(0,WIDTH+1,0)" } data { id 147 ssIdNumber 6 name "z" linkNode [142 146 148] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 148 ssIdNumber 7 name "B" linkNode [142 147 149] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_CUSTOM_INTEGER_TYPE primitive SF_INT16_TYPE expression "fixdt(89,1,16,0)" wordLength "WIDTH+1" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "fixdt(0,WIDTH+1,0)" } data { id 149 ssIdNumber 11 name "WIDTH" description "xcdfghb" linkNode [142 148 0] scope PARAMETER_DATA isNonTunable 1 machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE wordLength "8" fixpt { scalingMode SF_FIXPT_BINARY_POINT fractionLength "0" slope "2^0" bias "0" } } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 150 name "add2nmp/add2np" machine 1 chart 142 } target { id 151 name "sfun" description "Default Simulink S-Function Target." machine 1 linkNode [1 0 152] } target { id 152 name "slhdlc" codeFlags " comments=1 emitdescriptions=1" machine 1 linkNode [1 151 0] } }