# intrinsic delay at Load=0.1p GATE AND 1 Y = ( A * B ); PIN A NONINV 0.05 0.9494 0.2200 3.1600 0.1200 2.00 PIN B NONINV 0.05 0.9494 0.2200 3.1600 0.1200 2.00 GATE INV 1 Y = ! A; PIN A INV 0.04 1.0 0.07 3.1800 0.09 2.9000 GATE BUF 1 Y = A; PIN A NONINV 0.04 1.0 0.07 3.1800 0.09 2.9000 GATE OR 1 Y = (A + B); PIN A NONINV 0.09 1.0 0.85 2.97 0.74 2.91 PIN B NONINV 0.09 1.0 0.85 2.97 0.74 2.91 GATE XOR 1 Y = ((!A * B) + (A * !B)); PIN A UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91 PIN B UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91 GATE XNOR 1 Y = !((!A * B) + (A * !B)); PIN A UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91 PIN B UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91 GATE NAND 1 Y = ! (A * B); PIN A INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00 PIN B INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00 GATE NOR 1 Y = ! (A + B); PIN A INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500 PIN B INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500 GATE LOGIC0 0 O=CONST0; GATE LOGIC1 0 O=CONST1;