Генератор Verilog для матричного умножителя

Выберите разрядность значений:

Выберите размер матрицы A: x

Выберите размер матрицы B: x

Использовать цепочку сбросов (для алгоритма разделяй/властвуй):

Verilog матричного умножителя:

module SMM_3x3_3x3__3 (
// output matrix
c0_0, c0_1, c0_2, 
c1_0, c1_1, c1_2, 
c2_0, c2_1, c2_2, 
// input vectors
a0, a1, a2,  
b0, b1, b2,  
// clock_reset
clk,
res
);
	parameter width = 3;
	parameter out_width = 8;
	
	input clk, res;
	input [width-1:0] a0, a1, a2;
	input [width-1:0] b0, b1, b2;
	output [out_width-1:0] c0_0, c0_1, c0_2;
	output [out_width-1:0] c1_0, c1_1, c1_2;
	output [out_width-1:0] c2_0, c2_1, c2_2;
	
	// SHIFT REGISTERS
	wire [width-1:0] a0_sh, a1_sh, a2_sh; // wires for shifted a data
	wire [width-1:0] b0_sh, b1_sh, b2_sh; // wires for shifted b data
	// for A vector
	assign a0_sh = a0;
	shift_reg #(1, width) sha1 (a1_sh, a1, clk, res);
	shift_reg #(2, width) sha2 (a2_sh, a2, clk, res);
	// for B vector
	assign b0_sh = b0;
	shift_reg #(1, width) shb1 (b1_sh, b1, clk, res);
	shift_reg #(2, width) shb2 (b2_sh, b2, clk, res);

// MATRIX OF PROCESSING ELEMENTS
	wire [width-1:0] a0_0_out, a0_1_out, a0_2_out;
	wire [width-1:0] a1_0_out, a1_1_out, a1_2_out;
	wire [width-1:0] a2_0_out, a2_1_out, a2_2_out;

wire [width-1:0] b0_0_out, b0_1_out, b0_2_out;
	wire [width-1:0] b1_0_out, b1_1_out, b1_2_out;
	wire [width-1:0] b2_0_out, b2_1_out, b2_2_out;

// ROW 0
	PE #(width, width, out_width) pe0_0 (c0_0, a0_0_out, b0_0_out, a0_sh, b0_sh, clk, res);
	PE #(width, width, out_width) pe0_1 (c0_1, a0_1_out, b0_1_out, a0_0_out, b1_sh, clk, res);
	PE #(width, width, out_width) pe0_2 (c0_2, a0_2_out, b0_2_out, a0_1_out, b2_sh, clk, res);
	// ROW 1
	PE #(width, width, out_width) pe1_0 (c1_0, a1_0_out, b1_0_out, a1_sh, b0_0_out, clk, res);
	PE #(width, width, out_width) pe1_1 (c1_1, a1_1_out, b1_1_out, a1_0_out, b0_1_out, clk, res);
	PE #(width, width, out_width) pe1_2 (c1_2, a1_2_out, b1_2_out, a1_1_out, b0_2_out, clk, res);
	// ROW 2
	PE #(width, width, out_width) pe2_0 (c2_0, a2_0_out, b2_0_out, a2_sh, b1_0_out, clk, res);
	PE #(width, width, out_width) pe2_1 (c2_1, a2_1_out, b2_1_out, a2_0_out, b1_1_out, clk, res);
	PE #(width, width, out_width) pe2_2 (c2_2, a2_2_out, b2_2_out, a2_1_out, b1_2_out, clk, res);

endmodule

module PE(c, a_out, b_out, a, b, clk, res);
	parameter a_width = 3;
	parameter b_width = 3;
	parameter c_width = 8;
	
	input clk, res;
	input [a_width-1:0] a;
	input [b_width-1:0] b;
	output reg [a_width-1:0] a_out;
	output reg [b_width-1:0] b_out;
	output reg [c_width-1:0] c;
	
	wire [a_width+b_width-1:0] mult;
	
	assign mult = a*b;
	
	always @ (posedge clk or posedge res)
      if (res)
        begin
          a_out <= 0;
          b_out <= 0;
          c <= 0;
        end
      else 
        begin
          a_out <= a;
          b_out <= b;
          c <= c + mult;
        end
endmodule

module shift_reg (out, in, clk, res);
    parameter len = 3; // Number of stages (1 = this is a simple FF)
    parameter width = 3;  // Width of in / out

input clk, res;
    input [width-1:0] in;
    output [width-1:0] out;

reg [len*width-1:0] shreg;

always @(posedge clk or posedge res) begin
        if (res)
            shreg <= 0;
        else
            shreg <= {shreg, in};
    end

assign out = shreg[len*width-1:(len-1)*width];
endmodule

Тест-бенч:

module test_bench();
	
	// main testbench parameters
  	parameter verbose = 1;
  
  	// basic SMM parameters
	parameter width = 3;
	parameter out_width = 8;
	localparam MAX = 2**width;
	
	// One matrix multiplication takes n = (size)*3 - 4 clock cycles
	// First (size) cycles for feeding data
	// Last (size + 2) cycles for the rest calculus
	
	// connections to DUT
	// output matrix
	wire [out_width-1:0] c0_0, c0_1, c0_2;
	wire [out_width-1:0] c1_0, c1_1, c1_2;
	wire [out_width-1:0] c2_0, c2_1, c2_2;
	// input vectors
	reg [width-1:0] a0, a1, a2;
	reg [width-1:0] b0, b1, b2;
	// clock_reset
	reg clk, res;

// variables
	integer i, j, k, success_flag;
	reg [width-1:0] a [0:3-1] [0:3-1];
	reg [width-1:0] b [0:3-1] [0:3-1];
	reg [out_width-1:0] c [0:3-1] [0:3-1];
 
	// DUT instance
  	SMM_3x3_3x3__3 #(width, out_width) dut (
	// output matrix
	c0_0, c0_1, c0_2, 
	c1_0, c1_1, c1_2, 
	c2_0, c2_1, c2_2, 
	// input vectors
	a0, a1, a2,  
	b0, b1, b2,  
	// clock_reset
	clk,
	res
	);

// Generate (print) random matrices
	initial begin
		for (int i=0; i<=3-1; i++) 
			for (int j=0; j<=3-1; j++) begin
				a[i][j] = $urandom%(MAX);
				end
		for (int i=0; i<=3-1; i++) 
			for (int j=0; j<=3-1; j++) begin
				b[i][j] = $urandom%(MAX);
				end
		if (verbose)
			begin
			$display("------------A------------");
			for (int i=0; i<=3-1; i++) begin
				for (int j=0; j<=3-1; j++) 
					$write("%0d ", a[i][j]);
				$write("\n");
				end
			$display("------------B------------");
			for (int i=0; i<=3-1; i++) begin
				for (int j=0; j<=3-1; j++) 
					$write("%0d ", b[i][j]);
				$write("\n");
				end			
			end
	end
	
	
	// Calculate (print) golden out
	initial begin
		for (int i=0; i<=3-1; i++) 
			for (int j=0; j<=3-1; j++) begin
				c[i][j] = 0;
				for (int k=0; k<=3-1; k++)
					c[i][j] = c[i][j] + a[i][k]*b[k][j];
			end
		
		if (verbose) begin
			$display("------------C------------");
			for (int i=0; i<=3-1; i++) begin
				for (int j=0; j<=3-1; j++) 
					$write("%0d ", c[i][j]);
				$write("\n");
			end
		end
	end

// Simulation
	initial begin
		clk = 0;       // initial value of clock
		res = 1;       // initial value of reset
		#10 res = 0;   
		// Pass the data through systolic array
		for (i=0; i<=3-1; i=i+1) begin
			a0 = a[0][i];
			a1 = a[1][i];
			a2 = a[2][i];
			b0 = b[i][0];
			b1 = b[i][1];
			b2 = b[i][2];
			#10;
		end
		for (i=0; i<=3+3-3; i=i+1) begin
			a0 = 0;
			a1 = 0;
			a2 = 0;
			b0 = 0;
			b1 = 0;
			b2 = 0;
			#10;
		end
		// Check the result
		success_flag = 1;	
		if (verbose) begin
			$display("----------Output----------");
			$display("%0d %0d %0d", c0_0, c0_1, c0_2);
			$display("%0d %0d %0d", c1_0, c1_1, c1_2);
			$display("%0d %0d %0d", c2_0, c2_1, c2_2);
		end
		if ({c0_0, c0_1, c0_2} != {c[0][0], c[0][1], c[0][2]}) 
			success_flag = 0;
		if ({c1_0, c1_1, c1_2} != {c[1][0], c[1][1], c[1][2]}) 
			success_flag = 0;
		if ({c2_0, c2_1, c2_2} != {c[2][0], c[2][1], c[2][2]}) 
			success_flag = 0;
		if (success_flag)
			$display("SUCCESS MATRIX MULT WORKS FINE");
		else
			$display("ERROR: VERIFICATION FAILED. CHECK DESIGN.");
		
		$finish();
	end

// Clock generator
	always 
	  #5 clk = ~clk; // Toggle clock every 5 ticks
	
endmodule

Описание: Аппаратная реализация систолического матричного умножителя. На текущий момент вычисляет произведение квадратных матриц. Построен на основе матрицы вычислительных элементов и сдвиговых регистров. Матрица A подаётся по столбцам, матрица B - построчно. Полный цикл вычислений требует 3*n-4 тактов из которых n на загрузку обеих матриц - остальные на проведение вычислений.