Verilog generator for multi-input RNS adder

Adder type (see more at the bottom of the page):
Choose module (from 2 to 1024) :
Choose number of adder inputs (from 2 to 1024):
Create memory environment
Write Test Bench

Number of input bits: 5

- RNS pyramidal adder - based on the traditional two-input RNS adders grouped as a pyramid.
- RNS adder with correction at output - based on conventional multi-input adder. Output value is formed by efficient direct converter to RNS (modulo p).
- RNS adder with intermediate correction - based on conventional multi-input adders. Maximal number of adders in one block is restricted. Each block is followed by direct converter. Then comes the next set of adders, and so on.
- RNS serial adder - based on conventional two-input RNS adders placed in sequence one after another (this implemenation is not efficient as compared to pyramidal structure).
- Positional adder (for tests) - conventional positional multi-input adder for test purpose

Test results (to come soon)

Resume: the most efficient FPGA adder implementation is RNS adder with correction at output

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