Verilog generator for multi-input RNS adder

Adder type (see more at the bottom of the page):

Максимальное число элементов в позиционном сумматоре (от 2 до 1024):

Choose module (from 2 to 1024) :

Choose number of adder inputs (from 2 to 1024):

Create memory environment

Write Test Bench

Number of input bits: 5

module sum2_mod_17 (in1, in2, out);
	input [4:0] in1;
	input [4:0] in2;
	output reg [4:0] out;
	wire [5:0] w;
	assign w = in1 + in2;
	always @ (*)
	begin
		if (w < 17)
			out <= w;
		else
			out <= w - 17;
	end
endmodule

module sum16_mod_17 (in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, out);
	input [4:0] in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16;
	output [4:0] out;

	// Level 1
	wire [4:0] a0;
	sum2_mod_17 inst0 (in1, in2, a0);
	wire [4:0] a1;
	sum2_mod_17 inst1 (in3, in4, a1);
	wire [4:0] a2;
	sum2_mod_17 inst2 (in5, in6, a2);
	wire [4:0] a3;
	sum2_mod_17 inst3 (in7, in8, a3);
	wire [4:0] a4;
	sum2_mod_17 inst4 (in9, in10, a4);
	wire [4:0] a5;
	sum2_mod_17 inst5 (in11, in12, a5);
	wire [4:0] a6;
	sum2_mod_17 inst6 (in13, in14, a6);
	wire [4:0] a7;
	sum2_mod_17 inst7 (in15, in16, a7);
	// Level 2
	wire [4:0] a8;
	sum2_mod_17 inst8 (a0, a1, a8);
	wire [4:0] a9;
	sum2_mod_17 inst9 (a2, a3, a9);
	wire [4:0] a10;
	sum2_mod_17 inst10 (a4, a5, a10);
	wire [4:0] a11;
	sum2_mod_17 inst11 (a6, a7, a11);
	// Level 3
	wire [4:0] a12;
	sum2_mod_17 inst12 (a8, a9, a12);
	wire [4:0] a13;
	sum2_mod_17 inst13 (a10, a11, a13);
	// Level 4
	sum2_mod_17 inst14 (a12, a13, out);
endmodule

Description:
- RNS pyramidal adder - based on the traditional two-input RNS adders grouped as a pyramid.
- RNS adder with correction at output - based on conventional multi-input adder. Output value is formed by efficient direct converter to RNS (modulo p).
- RNS adder with intermediate correction - based on conventional multi-input adders. Maximal number of adders in one block is restricted. Each block is followed by direct converter. Then comes the next set of adders, and so on.
- RNS serial adder - based on conventional two-input RNS adders placed in sequence one after another (this implemenation is not efficient as compared to pyramidal structure).
- Positional adder (for tests) - conventional positional multi-input adder for test purpose

Test results (to come soon)

Resume: the most efficient FPGA adder implementation is RNS adder with correction at output